Semiconductor memory device

A semiconductor memory device comprising a memory cell array, the memory cell array comprising memory cells,

• the memory cell array comprising:
• first conductive layers stacked at a predetermined pitch in a first direction perpendicular to a substrate, the first conductive layers extending in a second direction parallel to the substrate;
• a memory layer provided in common on side surfaces of the first conductive layers;
• and
• a second conductive layer comprising a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction,
• a width in the second direction of the first side surface at a first position being smaller than a width in the second direction of the first side surface at a second position higher than the first position, and
• a thickness in the first direction of the first conductive layer at the first position being larger than a thickness in the first direction of the first conductive layer at the second position.

A semiconductor memory device comprising a memory cell array, the memory cell array comprising memory cells,

• the memory cell array comprising:
• first conductive layers stacked at a predetermined pitch in a first direction perpendicular to a substrate, the first conductive layers extending in a second direction parallel to the substrate;
• a memory layer provided in common on side surfaces of the first conductive layers;
• and
• a second conductive layer comprising a first side surface in contact with side surfaces of the first conductive layers via the memory layer, the second conductive layer extending in the first direction,
• a width in the second direction of the first side surface at a first position being smaller than a width in the second direction of the first side surface at a second position lower than the first position,
• a third direction extending in a direction perpendicular to the first and second directions, and
• a thickness in the third direction of the memory layer at the first position being larger than a thickness in the third direction of the memory layer at the second position.