Non-volatile memory device and method of manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorMutsumi OKAJIMA
Life of this patent
Estimating the term…
Abstract
According to one embodiment, there are provided a memory cell forming region, a first wiring hookup region in which first wirings extending in a first direction are formed by being drawn outside of the memory cell forming region, a second wiring hookup region which is disposed in a layer above the first wirings and in which second wirings extending in a second direction are formed by being drawn outside of the memory cell forming region, and a first dummy wiring connected to each of the second wirings. The first dummy wiring is disposed so that a sum of the area of the second wiring and the area of the first dummy wiring becomes the same in the respective second wirings.
Claims20
A non-volatile memory device comprising:
- a memory cell forming region having a memory cell array layer where a plurality of non-volatile memory cells are formed in a matrix shape;
- a first wiring hookup region in which a plurality of first wirings that are connected to the non-volatile memory cell in the memory cell forming region and extend in a first direction are formed by being drawn outside of the memory cell forming region;
- a second wiring hookup region in which a plurality of second wirings that are connected to the non-volatile memory cell in a layer above the first wirings in the memory cell forming region and extend in a second direction intersecting the first direction are formed by being drawn outside of the memory cell forming region;
- and
- a first dummy wiring connected to the second wiring, wherein
- the first dummy wiring is disposed so that a sum of the area of the second wiring and the area of the first dummy wiring in the memory cell forming region and in the second wiring hookup region becomes the same in the respective second wirings.
The non-volatile memory device according to claim wherein the first dummy wiring is disposed to an end of the second wiring opposite to the second wiring hookup region.
A method of manufacturing a non-volatile memory device including a plurality of first wirings extending in a first direction, a plurality of second wirings extending in a second direction intersecting the first direction, and a non-volatile memory cell array layer where a plurality of non-volatile memory cells are arranged at intersection portions of the first wirings and the second wirings so to be interposed, the method comprising:
- sequentially stacking a first wiring material layer which is to be the first wirings and a memory-layer constituting layer constituting the non-volatile memory cells above a substrate;
- etching the memory-layer constituting layer and the first wiring material layer to form a first pattern having a first line and space pattern extending in the first direction in the memory cell forming region and in a first wiring hookup region located adjacent to the memory cell forming region in the first direction and to remove the memory-layer constituting layer and the first wiring material layer in a second wiring hookup region located adjacent to the memory cell forming region in the second direction by dry etching;
- forming an interlayer insulating film so as to be embedded between line patterns constituting the first line and space pattern in the memory cell forming region and in the first wiring hookup region and so as to be formed in a region removed by dry etching in the second wiring hookup region;
- forming a second wiring material layer which is to be the second wiring on the interlayer insulating film and on the memory-layer constituting layer;
- and
- processing the second wiring material layer and the memory-layer constituting layer and the interlayer insulating film to form a second pattern having a second line and space pattern extending in the second direction and a first dummy pattern connected to each of respective line patterns constituting the second line and space pattern so that the respective line patterns have the same area in the memory cell forming region and in the second wiring hookup region and to remove the second wiring material layer and the memory-layer constituting layer in the first wiring hookup region by dry etching.
A method of manufacturing a non-volatile memory device including a plurality of first wirings extending in a first direction, a plurality of second wirings extending in a second direction intersecting the first direction, and a non-volatile memory cell array layer where a plurality of non-volatile memory cells are arranged at intersection portions of the first wirings and the second wirings so to be interposed, the method comprising:
- sequentially stacking a first wiring material layer which is to be the first wirings and a first memory-layer constituting layer constituting a non-volatile memory cell above a substrate;
- etching the first memory-layer constituting layer and the first wiring material layer to form a first pattern having a first line and space pattern extending in the first direction in the memory cell forming region and a first wiring hookup region located adjacent to the memory cell forming region in the first direction, and to remove the first memory-layer constituting layer and the first wiring material layer in a second wiring hookup region located adjacent to the memory cell forming region in the second direction by dry etching;
- forming a first interlayer insulating film so as to be embedded between line patterns constituting the first line and space pattern in the memory cell forming region and in the first wiring hookup region and so as to be formed in a region removed by dry etching in the second wiring hookup region;
- sequentially stacking a second wiring material layer which is to be the second wiring and a second memory-layer constituting layer constituting a non-volatile memory cell on the first interlayer insulating film and on the first memory-layer constituting layer;
- and
- processing the second memory-layer constituting layer and the second wiring material layer and the first memory-layer constituting layer and the first interlayer insulating film to form a second pattern having a second line and space pattern extending in the second direction and a first dummy pattern connected to each of the respective line patterns constituting the second line and space pattern so that the respective line patterns have the same area in the memory cell forming region and the second wiring hookup region, and to remove the second memory-layer constituting layer and the second wiring material layer and the first memory-layer constituting layer and the first interlayer insulating film in the first wiring hookup region by dry etching.
Dependencies are inferred from the claim text.