# US 2014/0208284 A1 · Method and system for designing 3d semiconductor package

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- Number: US 2014/0208284 A1
- Document ID: US20140208284A1
- Status: Published application
- Kind: A1
- Application number: 13/803,534
- Filed: 2013-03-14
- Published: 2014-07-24
- Earliest claimed: 2013-01-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Bo-Sun Hwang; Sung-Hee Yun; Jae-Hoon Jeong; Won-Cheol Lee; Tae-Heon Lee; Young-Hoe Cheon
- Web page: https://patentgrep.com/patent/US20140208284A1

## CPC

- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 30/333: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- G16Z 99/00: Subject matter not provided for in other main groups of this subclass
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G16Z: INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR SPECIFIC APPLICATION FIELDS, NOT OTHERWISE PROVIDED FOR

## Abstract

A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout.

## Claims

### Claim 1

A method for designing a 3D semiconductor package, comprising:
a special purpose processor receiving a first package layout parameter for a plurality of first terminals included in a first semiconductor package, a second package layout parameter for a plurality of second terminals included in a second semiconductor package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals to electrically connect terminals of the first semiconductor package to terminals of the second semiconductor package;
the special purpose processor generating a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters, wherein said generating a first wiring connection layout by applying a first process comprises generating an initial solution by applying a first sub-process to the first semiconductor package, second semiconductor package, and connection terminal layout parameters, and generating the first wiring connection layout by applying a second sub-process, which is different from the first sub-process, to the initial solution; and
the special purpose processor generating a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout, wherein the second process includes determining a first reference vector at a center of the first wiring connection layout, sequentially numbering the second terminals and the connection terminals by rotating the first reference vector in a clockwise direction or counterclockwise direction, and connecting the second terminals and the connection terminals having the same number to each other.

### Claim 2 (depends on 1)

The method of claim 1, wherein at least one of the first semiconductor package, second semiconductor package, and connection terminal layout parameters includes a size, number, shape and arrangement of the terminals, a pitch between the terminals, and a thickness of the first or second semiconductor package.

### Claim 3

(canceled)

### Claim 4 (depends on 1)

The method of claim 1, wherein the first sub-process includes a greedy process, and the second sub-process includes a genetic process.

### Claim 5 (depends on 4)

The method of claim 4, wherein said generating the first wiring connection layout by applying a second sub-process comprises generating the first wiring connection layout by using the second sub-process in a first range, and when adjusting the first range, a net length and a byte skew of the first wiring connection layout are adjusted.

### Claim 6

(canceled)

### Claim 7 (depends on 1)

The method of claim 1, wherein a direction of the first reference vector includes a direction from the center toward control address (CA) connection terminals among the connection terminals.

### Claim 8 (depends on 1)

The method of claim 1, wherein the initial solution includes n initial solutions, and the number n is a natural number smaller than or equal to the smallest number among the number of the first terminals, the number of the second terminals, and the number of the connection terminals, and
wherein said generating the first wiring connection layout comprises selecting m initial solutions, wherein m is a natural number satisfying m≦n, from among the n initial solutions, and generating the first wiring connection layout by applying the second sub-process to the m initial solutions.

### Claim 9 (depends on 8)

The method of claim 8, wherein said generating n initial solutions comprises selecting arbitrary n connection terminals from among the connection terminals, and generating the initial solution for each of the selected n connection terminals.

### Claim 10 (depends on 1)

The method of claim 1, further comprising, before generating the initial solution, generating a base substrate terminal layout parameter for a plurality of third terminals included in a base substrate disposed below the first semiconductor package, and designing a wiring between the first terminals and the third terminals by using the first and fourth layout parameters.

### Claim 11 (depends on 10)

The method of claim 10, wherein said designing a wiring between the first terminals and the third terminals comprises designing the wiring by using a greedy process.

### Claim 12 (depends on 1)

The method of claim 1, wherein the first semiconductor package includes an application processor (AP) chip, and the second package includes a memory chip.

### Claim 13

A special purpose processor, comprising:
a central processing unit; and
a storage which stores a module for designing a three-dimensional (3D) net assignment between a plurality of first terminals included in a first semiconductor package, a plurality of second terminals included in a second semiconductor package disposed above or below the first semiconductor package, and connection terminals connecting the first semiconductor package and the second semiconductor package by an operation of the central processing unit,
wherein the module comprises:
receiving a first package layout parameter for the first terminals, a second package layout parameter for the second terminals, and a connection terminal layout parameter for the connection terminals to electrically connect terminals of the first semiconductor package to terminals of the second semiconductor package;
generating an initial solution for a wiring between the first terminals, the second terminals and the connection terminals by applying a first sub-process to the first semiconductor package, second semiconductor package, and connection terminal layout parameters wherein said generating a first wiring connection layout by applying a first sub-process comprises generating an initial solution by applying a first sub-process to the first semiconductor package, second semiconductor package, and connection terminal layout parameters, and generating the first wiring connection layout by applying a second sub-process, which is different from the first sub-process, to the initial solution; and
generating a first wiring connection layout by applying a second sub-process to the initial solution, wherein the second sub process includes determining a first reference vector at a center of the first wiring connection layout, sequentially numbering the second terminals and the connection terminals by rotating the first reference vector in a clockwise direction or counterclockwise direction, and connecting the second terminals and the connection terminals having the same number to each other; and
designing the 3D net assignment from the first wiring connection layout by using a second process.

### Claim 14 (depends on 13)

The special purpose processor of claim 13, wherein the initial solution includes n initial solutions, and the number n is a natural number smaller than or equal to the smallest number among the number of the first terminals, the number of the second terminals, and the number of the connection terminals, and
wherein said generating a first wiring connection layout by applying a second sub-process comprises selecting m initial solutions, wherein m is a natural number satisfying m≦n, from among the n initial solutions, and generating the first wiring connection layout by applying the second sub-process to the m initial solutions.

### Claim 15 (depends on 13)

The special purpose processor of claim 13, wherein the module for designing the 3D net assignment further comprises, before generating the initial solution, receiving a base substrate terminal layout parameter for a plurality of third terminals included in a base substrate disposed below the first semiconductor package, and designing a wiring between the first terminals and the third terminals by using the first and fourth layout parameters.

### Claim 16

A three-dimensional semiconductor device, comprising:
a first semiconductor package, including first package terminals;
a second semiconductor package, including second package terminals; and
a substrate, including connection terminals, wherein first package terminals are electrically connected to second package terminals through connection terminals, the connection layout between first package terminals, second package terminals, and connection terminals determined by first and second processes, wherein the first process establishes an initial layout using a plurality of connection terminals as reference points, then refines the layout by selecting initial layouts having preferable net lengths or byte skews, and wherein the second process establishes connections between connection terminals and second package terminals by sweeping connection and second package terminals, numbering the respective terminals in the order in which they are swept, and connecting like-numbered second package terminals to liked-numbered connection terminals.

### Claim 17 (depends on 16)

The three-dimensional semiconductor device of claim 16, wherein the first process includes a greedy process.

### Claim 18 (depends on 16)

The three-dimensional semiconductor device of claim 16, wherein the first process employs first package, second package, and connection terminal layout parameters.

### Claim 19 (depends on 16)

The three-dimensional semiconductor device of claim 16, wherein the first process includes a genetic optimization process.

### Claim 20 (depends on 16)

The three-dimensional semiconductor device of claim 16, wherein the first process includes an optimization process that optimizes the initial layout by dividing the substrate into ranges and optimizing on a range-by-range basis.