# US 2014/0208282 A1 · Conflict detection for self-aligned multiple patterning compliance > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0208282 A1 - Document ID: US20140208282A1 - Status: Published application - Kind: A1 - Application number: 13/747,684 - Filed: 2013-01-23 - Published: 2014-07-24 - Earliest claimed: 2013-01-23 - Assignees: Taiwan Semiconductor Manufacturing Compnay, Ltd. - Inventors: Chin-Chang Hsu; HungLung Lin; Ying-Yu Shen; Wen-Ju Yang; Ken-Hsien Hsieh - Web page: https://patentgrep.com/patent/US20140208282A1 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G03F 7/70466: {Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature (stitching G03F7/70475)} - G03F 7/70475: {Stitching, i.e. connecting image fields to produce a device field, the field occupied by a device such as a memory chip, processor chip, CCD, flat panel display} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G) ## Abstract Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict. ## Claims ### Claim 1 A method for performing design layout, comprising: receiving an initial design layout associated with an electrical component; generating a conflict graph from the initial design layout, the conflict graph comprising one or more nodes connected by one or more edges, a node representing a polygon within the initial design layout, an edge comprising at least one of: a same-process edge connecting a first node generated by a first pattern process and a second node generated by the first pattern process, or a different-process edge connecting a third node generated by the first pattern process and a fourth node generated by a second pattern process; generating a cluster graph responsive to the conflict graph comprising the same-process edge, the cluster graph comprising a first node cluster representing the first node and the second node; and identifying a conflict associated with the initial design layout based upon the cluster graph, at least some of the method implemented at least in part via a processing unit. ### Claim 2 (depends on 1) The method of claim 1, the first node cluster representing the third node when at least one of the first node or the second node is connected to the third node by a second same-process edge. ### Claim 3 (depends on 1) The method of claim 1, the identifying a conflict comprising: identifying the conflict associated with the initial design layout based upon a loop within the cluster graph comprising an odd number of node clusters. ### Claim 4 (depends on 1) The method of claim 1, comprising: displaying the conflict within a visualization of the initial design layout. ### Claim 5 (depends on 4) The method of claim 4, comprising at least one of: providing a spacing constraint recommendation for the conflict; or applying the spacing constraint recommendation, resulting in removal of the different-process edge. ### Claim 6 (depends on 1) The method of claim 1, comprising: modifying the initial design layout to resolve the conflict and generate a modified initial design layout. ### Claim 7 (depends on 6) The method of claim 6, comprising: verifying that the modified initial design layout is self-aligned multiple patterning compliant. ### Claim 8 (depends on 4) The method of claim 4, the displaying the conflict comprising: displaying one or more mandrel pattern layers for the initial design layout, a mandrel pattern layer comprising mandrel surrounded at least in part by spacer; and displaying one or more trim pattern layers for the initial design layout. ### Claim 9 (depends on 1) The method of claim 1, the generating a conflict graph comprising: connecting the third node to the fourth node using the different-process edge based upon a space between a third polygon, represented by the third node, and a fourth polygon, represented by the fourth node, corresponding to a first spacing threshold range. ### Claim 10 (depends on 1) The method of claim 1, the generating a conflict graph comprising: connecting the first node to the second node using the same-process edge based upon a space between a first polygon, represented by the first node, and a second polygon, represented by the second node, corresponding to a second spacing threshold range. ### Claim 11 (depends on 6) The method of claim 6, comprising applying a trim mask to the modified initial design layout. ### Claim 12 (depends on 6) The method of claim 6, the modifying the initial design layout comprising: applying at least one of a min space rule, an island rule, an isolated trench rule, a corner-to-corner rule, or a flip assignment rule to the initial design layout. ### Claim at position 13 -20. (canceled) ### Claim 21 A system for performing design layout, comprising: a graph component configured to: receive an initial design layout associated with an electrical component; and generate a conflict graph from the initial design layout, the conflict graph comprising one or more nodes connected by one or more edges, a node representing a polygon within the initial design layout, an edge comprising at least one of: a same-process edge connecting a first node generated by a first pattern process and a second node generated by the first pattern process, or a different-process edge connecting a third node generated by the first pattern process and a fourth node generated by a second pattern process; and a conflict detection component configured to: generate a cluster graph responsive to the conflict graph comprising the same-process edge, the cluster graph comprising a first node cluster representing the first node and the second node; and identify a conflict associated with the initial design layout based upon the cluster graph. ### Claim 22 (depends on 21) The system of claim 21, the first node cluster representing the third node but not the fourth node. ### Claim 23 (depends on 21) The system of claim 21, the conflict detection component configured to: identify the conflict associated with the initial design layout based upon a loop within the cluster graph comprising an odd number of node clusters. ### Claim 24 (depends on 21) The system of claim 21, the conflict detection component configured to: display the conflict within a visualization of the initial design layout. ### Claim 25 (depends on 24) The system of claim 24, the conflict detection component configured to: provide a spacing constraint recommendation for the conflict; or apply the spacing constraint recommendation, resulting in removal of the different-process edge. ### Claim 26 (depends on 21) The system of claim 21, comprising: a conflict resolution component configured to: modify the initial design layout to resolve the conflict and generate a modified initial design layout. ### Claim 27 (depends on 24) The system of claim 24, the conflict detection component configured to: display one or more mandrel pattern layers for the initial design layout, a mandrel pattern layer comprising mandrel surrounded at least in part by spacer; and display one or more trim pattern layers for the initial design layout. ### Claim 28 A non-transitory computer readable medium comprising instructions which when executed perform a method for performing design layout, comprising: receiving an initial design layout associated with an electrical component; generating a conflict graph from the initial design layout, the conflict graph comprising one or more nodes connected by one or more edges, a node representing a polygon within the initial design layout, an edge comprising at least one of: a same-process edge connecting a first node generated by a first pattern process and a second node generated by the first pattern process, or a different-process edge connecting a third node generated by the first pattern process and a fourth node generated by a second pattern process; generating a cluster graph responsive to the conflict graph comprising the same-process edge, the cluster graph comprising a first node cluster representing the first node and the second node; and identifying a conflict associated with the initial design layout based upon the cluster graph.