# US 2014/0208187 A1 · Semiconductor apparatus and method of operating the same

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- Number: US 2014/0208187 A1
- Document ID: US20140208187A1
- Status: Published application
- Kind: A1
- Application number: 13/844,910
- Filed: 2013-03-16
- Published: 2014-07-24
- Earliest claimed: 2013-01-18
- Assignees: SK hynix Inc.
- Applicants: SK Hynix Inc.
- Inventors: Jun Rye RHO
- Web page: https://patentgrep.com/patent/US20140208187A1

## CPC

- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A semiconductor apparatus includes a memory device configured to include a buffer memory block and a main memory block, and to correct data read from the buffer memory block based on error information, and to perform a program loop to store corrected data in the main memory block, and a memory controller configured to perform an error checking and correction (ECC) operation on the data and to output the error information obtained through the ECC operation to the memory device.

## Claims

### Claim 1

A method of operating a semiconductor apparatus, the method comprising:
correcting first data read from a buffer memory block based on first error information obtained by performing a first error checking and correction (ECC) operation on the first data;
correcting second data read from the buffer memory block based on second error information obtained by performing a second ECC operation on the second data; and
performing a program loop on memory cells coupled to a selected word line in a main memory block based on the first data and the second data corrected by using the first error information and the second error information, respectively.

### Claim 2 (depends on 1)

The method of claim 1, wherein the semiconductor apparatus includes a memory controller and a memory device, the first ECC operation and the second ECC operation are performed by the memory controller, and the first data and the second data are corrected by the memory device.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first error information and the second error information are stored in the memory controller.

### Claim 4 (depends on 1)

The method of claim 1, wherein each of the first error information and the second error information include a location and a correction value of an error bit included in the first data and the second data, respectively.

### Claim 5 (depends on 1)

The method of claim 1, wherein each of the first error information and the second error information include error data having an error bit of 1 or 0 and a normal bit of 0 or 1 in the first and second data, respectively.

### Claim 6 (depends on 1)

The method of claim 1, further comprising, before the correcting of the first data:
performing the first ECC operation on the first data read from the buffer memory block;
storing the first error information obtained through the first ECC operation;
performing the second ECC operation on the second data from the buffer memory block; and
storing the second error information obtained through the second ECC operation.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
performing a first program loop to store the first data, on which the first ECC operation is performed, in the memory cells after the storing of the first error information; and
performing a second program loop to store the second data, on which the second ECC operation is performed, in the memory cells after the storing of the second error information.

### Claim 8

A method of operating a semiconductor apparatus, the method comprising:
correcting first data read from a buffer memory block based on first error information obtained by performing a first error checking and correction (ECC) operation on the first data;
correcting second data read from the buffer memory block based on second error information obtained by performing a second ECC operation on the second data;
correcting third data read from the buffer memory block based on third error information obtained by performing a third ECC operation on the third data; and
performing a program loop on memory cells coupled to a selected word line in a main memory block based on the first data to the third data corrected by using the first error information to the third error information, respectively.

### Claim 9 (depends on 8)

The method of claim 8, wherein the semiconductor apparatus includes a memory controller and a memory device, the first ECC to the third ECC operations are performed by the memory controller, and the first data to the third data are corrected by the memory device.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first error information to the third error information are stored in the memory controller.

### Claim 11 (depends on 8)

The method of claim 8, wherein each of the first error information to the third error information include a location and a correction value of an error bit included in the first data to the third data, respectively.

### Claim 12 (depends on 8)

The method of claim 8, wherein each of the first error information to the third error information include error data having an error bit of 1 or 0 and a normal bit of 0 or 1 in the first data to the third data, respectively.

### Claim 13 (depends on 8)

The method of claim 8, further comprising, before correcting the first data:
performing the first ECC operation on the first data read from the buffer memory block;
storing the first error information obtained through the first ECC operation;
performing the second ECC operation on the second data read from the buffer memory block;
storing the second error information obtained through the second ECC operation;
performing the third ECC operation on the third data read from the buffer memory block; and
storing the third error information obtained by performing the third ECC operation.

### Claim 14

A semiconductor apparatus, comprising:
a memory device configured to include a buffer memory block and a main memory block, and to correct data read from the buffer memory block based on error information, and to perform a program loop to store corrected data in the main memory block; and
a memory controller configured to perform an error checking and correction (ECC) operation on the data and to output the error information obtained through the ECC operation to the memory device.

### Claim 15 (depends on 14)

The semiconductor apparatus of claim 14, wherein the memory device further comprises:
a data change circuit configured to correct the data based on the error information; and
a read/write circuit configured to read the data from the buffer memory block and store the corrected data in the main memory block.

### Claim 16 (depends on 14)

The semiconductor apparatus of claim 14, wherein the memory controller comprises:
an ECC circuit configured to perform the ECC operation to generate the error information; and
a storage configured to store the error information.

### Claim 17 (depends on 14)

The semiconductor apparatus of claim 14, wherein the error information includes a location and a correction value of an error bit included in the data.

### Claim 18 (depends on 14)

The semiconductor apparatus of claim 14, wherein the error information includes error data having an error bit of 1 or 0 or a normal bit of 0 or 1 in the data.

### Claim 19 (depends on 14)

The semiconductor apparatus of claim 14, wherein the program loop includes an LSB program loop, an MSB program loop, and a re-program loop when the data include LSB data and MSB data, or
the program loop includes the LSB program loop, a CSB program loop, and the MSB program loop when the data include LSB data, CSB data, and the MSB data.

### Claim 20 (depends on 14)

The semiconductor apparatus of claim 14, wherein the memory device is configured to output the data from the buffer memory block, when the memory controller performs the ECC operation and stores the error information.