# US 2014/0208181 A1 · Zero sum signaling in a digital system environment > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0208181 A1 - Document ID: US20140208181A1 - Status: Published application - Kind: A1 - Application number: 14/125,292 - Filed: 2012-06-08 - Published: 2014-07-24 - Earliest claimed: 2011-06-10 - Assignees: Mayo Foundation for Medical Education and Research - Inventors: Erik S. Daniel; Robert W. Techentin - Web page: https://patentgrep.com/patent/US20140208181A1 ## CPC - H04L 1/004: {by using forward error control (H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00)} - G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's - G06F 13/423: {with synchronous protocol} - H03M 13/51: Constant weight codes; n-out-of-m codes; Berger codes - H04L 1/0042: {Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence)} - H04L 25/14: Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} - H04L 25/4908: {using mBnB codes} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Zero sum signaling schemes utilize coding across data words to allow the use of single-ended buffers while mitigating simultaneous switching noise (SSN) in digital systems. Zero sum signaling may include balanced zero sum coding (target disparity=0) and nearly balanced zero sum coding (target disparity=±d). Zero sum signaling may reduce simultaneous switching noise as compared to single-ended signaling while allowing a reduction in the number of physical channels (e.g. circuit board traces) by nearly a factor of two as compared to differential signaling. ## Claims ### Claim 1 (canceled) ### Claim 2 (canceled) ### Claim 3 (canceled) ### Claim 4 A system comprising: a plurality of devices that communicate using n-bit data words; a plurality of encoders, each associated with a different one of the plurality of devices, and each of which receives an n-bit data word from the associated device and encodes the n-bit data word into a corresponding (n+p)-bit data word comprised of an n-bit modified data word and a p-bit parity word, the n-bit modified data word having a number of ones and a number of zeroes, wherein the number of ones is within a disparity ±d as compared to the number of zeroes; a plurality of interconnects that route the (n+p)-bit modified data words between the plurality of devices; and a plurality of decoders, each associated with a different one of the plurality of devices, and each of which decodes one or more of the (n+p)-bit modified data words into the corresponding n-bit data words for receipt by the associated one of the plurality of devices. ### Claim 5 (depends on 4) The system of claim 4 wherein the disparity d is any positive integer. ### Claim 6 (depends on 4) The system of claim 4 wherein the disparity d is one of ±2 or ±4. ### Claim 7 (depends on 4) The system of claim 4 wherein at least one of the plurality of devices is a processor and at least one of the plurality of devices is a memory. ### Claim 8 A method comprising: generating an n-bit data word at a first device; encoding the n-bit data word into a corresponding (n+p)-bit data word comprised of an n-bit modified data word and a p-bit parity word, the n-bit modified data word having a number of ones and a number of zeroes, wherein the number of ones is within a disparity ±d as compared to the number of zeroes; transmitting the (n+p)-bit data word from the first device to a second device; and decoding the (n+p)-bit data word into the corresponding n-bit data word for receipt by the second device. ### Claim 9 (depends on 4) The system of claim 4 wherein the disparity ±d equals zero. ### Claim 10 (depends on 4) The system of claim 4 wherein the (n+p)-bit data word is a balanced (n+p)-bit data word, and the n-bit modified data word includes an equal number of ones and zeroes. ### Claim 11 (depends on 4) The system of claim 4 wherein a number of interconnects in the plurality of interconnects is relatively lower when the disparity d is non-zero as compared to when disparity ±d equals zero. ### Claim 12 (depends on 4) The system of claim 4 wherein the number of bits p in the p-bit parity word decreases as an absolute value of the disparity ±d increases. ### Claim 13 (depends on 4) The system of claim 4 wherein the encoder successively complements one bit of the n-bit data word until the n-bit modified data word having the number of ones within the disparity ±d as compared to the number of zeroes code is achieved. ### Claim 14 (depends on 13) The system of claim 13 wherein the encoder assigns the p-bit parity word based on how many bits of the n-bit data word are complemented to achieve the n-bit modified data word having a number of ones within the disparity ±d as compared to the number of zeroes. ### Claim 15 (depends on 8) The method of claim 8 wherein encoding the n-bit data word into a corresponding (n+p)-bit data word further includes successively complementing one bit of the n-bit data word until the n-bit modified data word having a number of ones within the disparity ±d as compared to the number of zeroes code is achieved. ### Claim 16 (depends on 15) The method of claim 15 further comprising assigning the p-bit parity word based on how many bits of the n-bit data word are complemented to achieve the n-bit modified data word having a number of ones within the disparity ±d as compared to the number of zeroes. ### Claim 17 (depends on 8) The method of claim 8 wherein the number of bits p in the p-bit parity word goes down as the absolute value of the disparity d increases. ### Claim 18 A system comprising: a first device and a second device that communicate using n-bit data words; an encoder associated with the first processing element that receives an n-bit data word from the first processing element and encodes the n-bit data word into a corresponding (n+p)-bit data word comprised of an n-bit modified data word and a p-bit parity word, the n-bit modified data word having a number of ones and a number of zeroes, wherein the number of ones is within a disparity ±d as compared to the number of zeroes; and a decoder associated with the second processing element that decodes the (n+p)-bit data word into the corresponding n-bit data word for receipt by a second processing element. ### Claim 19 (depends on 18) The system of claim 18 wherein the disparity ±d is any integer. ### Claim 20 (depends on 18) The system of claim 18 wherein the disparity ±d is one of ±2 or ±4. ### Claim 21 (depends on 18) The system of claim 18 wherein the first device is one of a processing element and a memory.