# US 2014/0208178 A1 · Circuit and Method for Measuring Delays between Edges of Signals of a Circuit

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- Number: US 2014/0208178 A1
- Document ID: US20140208178A1
- Status: Published application
- Kind: A1
- Application number: 14/222,362
- Filed: 2014-03-21
- Published: 2014-07-24
- Earliest claimed: 2010-02-15
- Assignees: Mentor Graphics Corporation
- Applicants: Mentor Graphics Corporation
- Inventors: Stephen Kenneth Sunter
- Web page: https://patentgrep.com/patent/US20140208178A1

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318577: {AC testing, e.g. current testing, burn-in}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

Various aspects of the present invention relate to techniques of measuring delays between edges of signals of a circuit. Alternating signals, synchronous to a first clock, are supplied to a plurality of nodes of the circuit. First samples of a plurality of signals associated with the alternating signals are captured using a first capture clock, of which sampling instants are synchronous to a second clock. Second samples of the first samples are then captured using a second capture clock, of which sampling instants are also synchronous to the second clock. The captured second samples are conveyed via a shift register to a plurality of modulo counters. The measured signal delay includes a timing skew associated with the first clock and a timing skew of the first capture clock but not a timing skew of the second capture clock.

## Claims

### Claim 1

A circuit for measuring a signal delay between an edge of a first alternating signal supplied to a first node of a circuit-under-test (CUT) and an edge of a second alternating signal supplied to a second node of the CUT, the first and second alternating signals being synchronous to a first clock, the circuit comprising:
means for capturing, controlled by a first capture clock, first samples of signals associated with the first and second alternating signals, the first capture clock's sampling instants being synchronous to a second clock and having a timing skew included in the signal delay measurement, the second clock being coherent to the first clock;
means for capturing, controlled by a second capture clock, second samples of the first samples, the second capture clock's sampling instants being synchronous to the second clock and having a timing skew not included in the signal delay measurement; and
means for conveying the second samples via a shift register to a plurality of modulo counters.

### Claim 2 (depends on 1)

The circuit recited in claim 1, wherein each of the modulo counters has a modulo base that is a fraction of or an integer multiple of the number of clock cycles in a beat period, the beat period being the smallest integer number of cycles of the first clock that has a time interval equal to an interval of a different integer number of cycles of the second clock.

### Claim 3 (depends on 2)

The circuit recited in claim 2, wherein the modulo counters comprise:
a first modulo counter selectively enabled to count samples between when a first edge is detected in the second samples conveyed from the first node to the modulo counter and a predetermined measurement end time; and
a second modulo counter selectively enabled to count samples between when a first edge is detected in the second samples conveyed from the second node to the modulo counter and a predetermined measurement end time;
and wherein the signal delay being proportional to a difference between counts of the first and second modulo counters.

### Claim 4 (depends on 1)

The circuit recited in claim 1, wherein the signal delay comprises a timing skew between the first and second alternating signals.

### Claim 5 (depends on 1)

The circuit recited in claim 1, further comprises:
means for logic values shifted in the shift register to selectively enable generation of the alternating signal at each node.

### Claim 6

A method for measuring delays between signal edges at nodes of a circuit, comprising:
supplying alternating signals to a plurality of nodes, the alternating signals being synchronous to a first clock;
capturing, controlled by a first capture clock, first samples of a plurality of signals associated with the alternating signals, each signal in the plurality of signals being associated with a node in the plurality of nodes, the first capture clock's sampling instants being synchronous to a second clock and having a timing skew included in the signal delay measurement, the second clock being coherent to the first clock;
capturing, controlled by a second capture clock, second samples of the first samples, the second capture clock's sampling instants being synchronous to the second clock and having a timing skew not included in the signal delay measurement; and
conveying the second samples via a shift register to a plurality of modulo counters.

### Claim 7 (depends on 6)

The method recited in claim 6, wherein each of the plurality of modulo counters having a modulo base that is a fraction of or an integer multiple of the number of clock cycles in a beat period, the beat period being the smallest integer number of cycles of the first clock that has a time interval equal to an interval of a different integer number of cycles of the second clock.