# US 2014/0208165 A1 · Multi-core device, test device, and method of diagnosing failure

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- Number: US 2014/0208165 A1
- Document ID: US20140208165A1
- Status: Published application
- Kind: A1
- Application number: 14/158,170
- Filed: 2014-01-17
- Published: 2014-07-24
- Earliest claimed: 2013-01-18
- Assignees: Industry-Academic Cooperation Foundation, Yonsei University
- Applicants: Industry-Academic Cooperation Foundation, Yonsei University
- Inventors: Sungho KANG; Taewoo HAN
- Web page: https://patentgrep.com/patent/US20140208165A1

## CPC

- G06F 11/2242: {in multi-processor systems, e.g. one processor becoming the primary tester (G06F11/2736 takes precedence)}
- G06F 11/267: Reconfiguring circuits for testing, e.g. LSSD, partitioning
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Provided is a multi-core device. The multi-core device includes: a plurality of cores outputting a test response value by receiving a test pattern value; a majority analyzer outputting a value corresponding to a majority of the test response value by analyzing the test response value; and a determination unit determining a core outputting a test response value different from the value corresponding to the majority among the plurality of cores.

## Claims

### Claim 1

A multi-core device comprising:
a plurality of cores outputting a test response value by receiving a test pattern value;
a majority analyzer outputting a value corresponding to a majority of the test response value by analyzing the test response value; and
a determination unit determining a core outputting a test response value different from the value corresponding to the majority among the plurality of cores.

### Claim 2 (depends on 1)

The multi-core device of claim 1, wherein the plurality of cores have the same circuit structure.

### Claim 3 (depends on 1)

The multi-core device of claim 1, wherein the plurality of cores receive the same test pattern value.

### Claim 4 (depends on 1)

The multi-core device of claim 1, wherein the plurality of cores receive the test pattern value simultaneously.

### Claim 5 (depends on 1)

The multi-core device of claim 1, wherein each of the plurality of cores comprises at least one scan chain.

### Claim 6 (depends on 5)

The multi-core device of claim 5, wherein the majority analyzer receives a test response value that the same scan chains in the plurality of cores output.

### Claim 7 (depends on 1)

The multi-core device of claim 1, wherein the majority analyzer comprises:
an adder adding the test response value; and
a comparator comparing an added value and half the number of cores.

### Claim 8 (depends on 7)

The multi-core device of claim 7, wherein the comparator outputs 1 when the added value is greater than half the number of cores and outputs 0 when the added value is less than half the number of cores.

### Claim 9 (depends on 8)

The multi-core device of claim 8, wherein the comparator outputs one of 1 and 0 when the added value is identical to half the number of cores.

### Claim 10 (depends on 1)

The multi-core device of claim 1, wherein the majority analyzer outputs the value corresponding to the majority to a test device connected to the multi-core device.

### Claim 11 (depends on 1)

The multi-core device of claim 1, wherein the determination unit comprises an XOR gate performing an XOR operation on the test response value and the value corresponding to the majority.

### Claim 12 (depends on 11)

The multi-core device of claim 11, wherein the determination unit further comprises a register storing an output value of the XOR gate.

### Claim 13 (depends on 5)

The multi-core device of claim 5, wherein if each core comprises a plurality of scan chains, the determination unit comprises:
a plurality of XOR gates performing an XOR operation on a test response value outputted from each scan chain and a value corresponding to a majority for a corresponding scan chain; and
an OR gate performing an OR operation on output values of the plurality of XOR gates.

### Claim 14 (depends on 13)

The multi-core device of claim 13, wherein the determination unit further comprises a register storing an output value of the OR gate.

### Claim 15 (depends on 1)

The multi-core device of claim 1, further comprising:
a first adjustment unit adjusting an applying time of the test pattern value to allow the test pattern value to be sequentially inputted to each core;
a second adjustment unit adjusting an applying time of the test response value to allow the test response value to be simultaneously inputted to the majority analyzer; and
a third adjustment unit adjusting an applying time of the test response value to allow the test response value to be simultaneously inputted to the determination unit.

### Claim 16 (depends on 15)

The multi-core device of claim 15, wherein the first adjustment unit comprises a buffer connected to an input terminal of a core.

### Claim 17 (depends on 15)

The multi-core device of claim 15, wherein the second adjustment unit comprises a buffer connected between an output terminal of a core and an input terminal of the majority analyzer.

### Claim 18 (depends on 15)

The multi-core device of claim 15, wherein the third adjustment unit comprises a buffer connected between an output terminal of a core and an input terminal of the determination unit.

### Claim 19 (depends on 16)

The multi-core device of claim 16, wherein the buffer comprises a D flip-flop.

### Claim 20 (depends on 15)

The multi-core device of claim 15, wherein the second adjustment unit comprises a counter counting the number of 1's among test response values from a core to which the test pattern value is inputted first to a core to which the test pattern value is inputted second from the last.

### Claim 21 (depends on 20)

The multi-core device of claim 20, wherein the majority analyzer receives a test response value of a core to which the test pattern value is inputted last and an output value of the counter.

### Claim 22 (depends on 21)

The multi-core device of claim 21, wherein the majority analyzer outputs 1 if the output value of the counter is greater than half the number of cores, outputs 0 if the output value of the counter is less than half the number of cores, and outputs a test response value of a core to which the test pattern value is inputted last if the output value of the counter is identical to half the number of cores.

### Claim 23

A test device comprising:
a test pattern value input unit inputting a test pattern value to a plurality of cores;
a majority value receiving unit receiving a value corresponding to a majority of a test response value outputted from the plurality of cores in response to the test pattern value;
a comparison unit comparing the value corresponding to the majority and an expected value corresponding to the test pattern value; and
a diagnosis unit diagnosing a failure of the plurality of cores according to a comparison result of the comparison unit.

### Claim 24 (depends on 23)

The test device of claim 23, wherein the test pattern value input unit inputs the same test pattern value to the plurality of cores.

### Claim 25 (depends on 23)

The test device of claim 23, wherein the test pattern value input unit simultaneously inputs the test pattern value to the plurality of cores.

### Claim 26 (depends on 23)

The test device of claim 23, wherein the comparison unit outputs a signal notifying that the value corresponding to the majority is identical to the expected value.

### Claim 27 (depends on 23)

The test device of claim 23, wherein the diagnosis unit determines the plurality of cores as failed if the value corresponding to the majority is different from the expected value.

### Claim 28 (depends on 23)

The test device of claim 23, further comprising a comparison data receiving unit receiving comparison data obtained by comparing a test response value outputted from each core and the value corresponding to the majority.

### Claim 29 (depends on 28)

The test device of claim 28, wherein the diagnosis unit diagnoses a failure of each core on the basis of the comparison data when the value corresponding to the majority is identical to the expected value.

### Claim 30 (depends on 29)

The test device of claim 29, wherein the diagnosis unit determines a core outputting a test response value identical to the value corresponding to the majority as normal and determines a core outputting a test response value different from the value corresponding to the majority as failed.

### Claim 31 (depends on 28)

The test device of claim 28, wherein the diagnosis unit determines the plurality of cores as failed if the number of cores outputting a test response value identical to the value corresponding to the majority is identical to the number of cores outputting a test response value different from the value corresponding to the majority.

### Claim 32

A failure diagnosing method comprising:
inputting a test pattern value to a plurality of cores;
obtaining a value corresponding to a majority of a test response value outputted in response to the test pattern value;
comparing the value corresponding to the majority and an expected value corresponding to the test pattern value; and
diagnosing a failure of the plurality of cores according to a comparison result.

### Claim 33 (depends on 32)

The method of claim 32, wherein the diagnosing of the failure comprises determining the plurality of cores as failed when the value corresponding to the majority is different from the expected value.

### Claim 34 (depends on 32)

The method of claim 32, further comprising obtaining comparison data resulting from comparing a test response value outputted from each core and the value corresponding to the majority.

### Claim 35 (depends on 34)

The method of claim 34, wherein the diagnosing of the failure comprises separately diagnosing a failure of each core on the basis of the comparison data if the value corresponding to the majority is identical to the expected value.

### Claim 36 (depends on 35)

The method of claim 35, wherein the diagnosing of the failure separately comprises:
determining a core outputting a test response value identical to the value corresponding to the majority as normal; and
determining a core outputting a test response value different from the value corresponding to the majority as failed.

### Claim 37 (depends on 35)

The method of claim 35, wherein the diagnosing of the failure separately further comprises determining the plurality of cores as failed if the number of cores outputting a test response value identical to the value corresponding to the majority is identical to the number of cores outputting a test response value different from the value corresponding to the majority.

### Claim 38 (depends on 32)

A computer readable recording medium having a program recorded thereon, which implements a method of claim 32.