# US 2014/0208162 A1 · Generation of simulated errors for high-level system validation

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- Number: US 2014/0208162 A1
- Document ID: US20140208162A1
- Status: Published application
- Kind: A1
- Application number: 14/223,493
- Filed: 2014-03-24
- Published: 2014-07-24
- Earliest claimed: 2008-03-24
- Assignees: Emulex Corporation
- Applicants: Emulex Corporation
- Inventors: Bruce Gregory Warren; Carl Joseph Mies; William Eugene Morgan; William Patrick Goodwin
- Web page: https://patentgrep.com/patent/US20140208162A1

## CPC

- G06F 11/261: {by simulating additional hardware, e.g. fault simulation}
- G06F 11/263: Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers}
- G06F 11/3696: {Methods or tools to render software testable}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A device, integrated circuit and method for generating simulated errors are disclosed. In the disclosed device, integrated circuit and method, an original data value is read from a memory. The original data value is intercepted by the integrated circuit. The integrated circuit is operable to virtualize an error in the original data value to generate a modified data value. The integrated circuit is also operable to generate an interrupt according to the virtualization. This disclosure may be particularly useful for high-level memory validation.

## Claims

### Claim 1

A device comprising:
logic operable to request information concerning an address of a storage, the requested information corresponding to original data of the storage; and
an integrated circuit operably coupled to the processor, the integrated circuit operable to:
intercept the original data,
virtualize an error in the original data by generating modified data, and
generate an interrupt according to the virtualized error.

### Claim at position 2

2-29. (canceled)

### Claim 30 (depends on 1)

The device of claim 1, wherein the device comprises the storage.

### Claim 31 (depends on 1)

The device of claim 1, wherein the original data comprises an original read value.

### Claim 32 (depends on 1)

The device of claim 1, wherein the integrated circuit comprises modify logic coupled to the storage, the storage storing an original read value.

### Claim 33 (depends on 32)

The device of claim 32, wherein the modify logic is operable to modify the original read value by error data, thereby generating the modified data to virtualize the error in the original data.

### Claim 34 (depends on 1)

The device of claim 1, wherein the integrated circuit comprises selection logic operable to select either the modified data or the original data according to a comparison between a stored address data and a requested address.

### Claim 35 (depends on 1)

The device of claim 1, wherein the interrupt indicates that the modified data is selected.

### Claim 36 (depends on 1)

The device of claim 1, wherein the interrupt is delayed by a predetermined delay time.

### Claim 37 (depends on 1)

The device of claim 1, wherein the virtualized error in the original data is virtualized according to a location in a bit mask register.

### Claim 38 (depends on 1)

The device of claim 1, wherein the device comprises a register operable to store error data, wherein the modified data is generated based on the error data,
wherein the register is within a closed system and the error data of the register is programmable from outside the closed system.

### Claim 39

A method comprising:
accessing an original data value from a storage;
intercepting the original data value by an integrated circuit;
virtualizing an error in the original data value by generating a modified data value; and
generating an interrupt according to the virtualized error.

### Claim 40 (depends on 39)

The method of claim 39, wherein virtualizing an error in the original data value comprises modifying the original data value by error data.

### Claim 41 (depends on 39)

The method of claim 39, wherein the method comprises selecting either the modified data value or the original data value according to a comparison between a stored address data and a requested address.

### Claim 42 (depends on 39)

The method of claim 39, wherein the interrupt indicates that the modified data value is selected.

### Claim 43 (depends on 39)

The method of claim 39, wherein the method comprises delaying the interrupt by a predetermined delay time.

### Claim 44 (depends on 39)

The method of claim 39, wherein the virtualized error in the original data value is virtualized according to a location in a bit mask register.

### Claim 45 (depends on 39)

The method of claim 39, wherein the modified data value is generated based on error data programmed from outside a closed system.

### Claim 46

An integrated circuit comprising:
access logic operable to access an original data value from a storage;
intercept logic operable to intercept the original data value;
virtualization logic operable to virtualize an error in the original data value by producing a modified data value; and
interrupt logic operable to generate an interrupt according to the virtualized error.

### Claim 47 (depends on 46)

The integrated circuit of claim 46, wherein the virtualization logic is within a closed system, wherein the virtualization logic is operable to be programmed from outside the closed system.

### Claim 48 (depends on 46)

The integrated circuit of claim 46, wherein the interrupt logic is operable to delay the interrupt by a predetermined amount of time.