# US 2014/0208156 A1 · Memory access methods and apparatus

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- Number: US 2014/0208156 A1
- Document ID: US20140208156A1
- Status: Published application
- Kind: A1
- Application number: 13/387,714
- Filed: 2011-01-27
- Published: 2014-07-24
- Earliest claimed: 2010-01-28
- Assignees: Hewlett Packard Enterprise Development LP
- Inventors: Naveen Muralimanohar; Aniruddha Udipi; Chatterjee Niladrish; Balasubramonian Rajeev; Alan Lynn Davis; Norman Paul Jouppi
- Web page: https://patentgrep.com/patent/US20140208156A1

## CPC

- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0673: {Single storage device}
- G06F 11/1088: {Reconstruction on already foreseen single or plurality of spare disks}
- G06F 12/0893: Caches characterised by their organisation or structure
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 11/4082: {Address Buffers; level conversion circuits}
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 2212/1028: Power efficiency
- G06F 2212/3042: being part of a memory device, e.g. cache DRAM
- G06F 2212/305: being part of a memory device, e.g. cache DRAM
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A disclosed example apparatus includes a row address register (412) to store a row address corresponding to a row (608) in a memory array (602). The example apparatus also includes a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.

## Claims

### Claim 1

A memory, comprising:
a row address register (412) to store a row address corresponding to a row (608) in a memory array (602);
a row decoder (604) coupled to the row address register to assert a signal on a wordline (704) of the row after the memory receives a column address; and
a column decoder (606) to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.

### Claim 2 (depends on 1)

A memory as defined in claim 1, further comprising an address buffer (406) to latch the row address received from a memory controller (102) and send the row address to the row address register and to latch the column address and send the column address to a column address register (414) of the memory to facilitate concurrently decoding the row address and the column address at the memory.

### Claim 3 (depends on 2)

A memory as defined in claim 2, wherein the memory is a first memory, the address buffer is located external to the memory on a memory module (400) containing the memory and a second memory, the address buffer to send the row and column addresses to the first memory and the second memory.

### Claim 4 (depends on 1)

A memory as defined in claim 1, wherein the portion of the row includes a cache line segment (610) that forms a cache line addressed by the row and column addresses.

### Claim 5 (depends on 4)

A memory as defined in claim 4, wherein the row and column decoders selectively activate a second portion of the memory array based on the same row and column addresses, the second portion containing a second cache line segment to form the cache line, and the row and column decoders selectively activating additional portions until the entire cache line is output from a memory module (400) containing the memory.

### Claim 6 (depends on 5)

A memory as defined in claim 5, wherein the portion and the second portion are located in a corresponding row across the memory and a second memory of the memory module.

### Claim 7 (depends on 4)

A memory as defined in claim 4, wherein the memory is a first memory, the first memory is located on a memory module containing a second memory, and a second cache line segment comprising part of the cache line is activated in the second memory and output by the memory module in response to the row and column addresses.

### Claim 8 (depends on 1)

A memory as defined in claim 1, wherein the row decoder is to assert a first signal on the wordline connected to a first input of a logic gate (712), the column decoder is to assert a second signal at a second input of the logic gate, of the first and second signals to cause the logic gate to activate the portion of the row without activating a second portion of the row.

### Claim 9 (depends on 1)

A memory as defined in claim 1, wherein the memory is a dynamic random access memory chip.

### Claim 10 (depends on 1)

A memory as defined in claim 1, wherein the memory is located on one of a dual inline memory module (DIMM) (200) containing a second memory or a 3D stack memory module (300) containing the second memory.

### Claim 11

A memory module, comprising:
a first memory (402f) having a first row (608);
a second memory (402a) having a second row; and
an address buffer (406) to latch a row address and a column address and forward the row and column addresses to the first and second memories, the first memory to selectively activate a first portion of the first row and the second memory to selectively activate a second portion of the second row in response to the row and column addresses, the first portion and the second portion activated without activating other portions of the first and second rows.

### Claim 12 (depends on 11)

A memory module as defined in claim 11, wherein the first portion of the first row is a first cache line segment (610) and the second portion of the second row is a second cache line segment, the first and second memories to output the first and second portions to form a cache line.

### Claim 13 (depends on 11)

A memory module as defined in claim 11, wherein the first and second memories selectively activate portions of third and fourth rows respectively located in the first and second memories based on the same row and column addresses, the portions respectively containing third and fourth cache line segments to form the cache line, and the first and second memories selectively activating the portions of the third and fourth rows until an entirety of the cache line is output from the memory module (400).

### Claim 14 (depends on 11)

A memory module as defined in claim 11 structured as one of a dual inline memory module (DIMM) or a 3D stack memory module (300) including the first and second memories.

### Claim 15 (depends on 11)

A memory module as defined in claim 11, wherein the first memory includes a row decoder (604) and a column decoder (606), the row decoder to assert a first signal on a main wordline (704) connected to a first input of a logic gate (712), the column decoder to assert a second signal at a second input of the logic gate, the first and second signals to cause the logic gate to activate the first portion of the first row exclusive of other portions of the first row.

### Claim 16

A memory, comprising:
a data interface (816, 902, 1004); and
an integrated circuit memory die (806g) in communication with the data interface, the integrated circuit memory die comprising:
a plurality of banks (808);
a plurality of subarrays (810a, 810b) in each bank; and
bitlines (812) in each bank, first ones of the bitlines corresponding to a first one of the banks being addressable to access an entire cache line in a single one of the subarrays of the first bank.

### Claim 17 (depends on 16)

A memory as defined in claim 16, further comprising an address buffer (910, 1010, 1106) to latch row and column addresses to facilitate concurrently decoding the row and column addresses to read out the entire cache line from the single one of the subarrays.

### Claim 18 (depends on 17)

A memory as defined in claim 17, wherein the address buffer is external to the integrated circuit memory die and located on a memory module (200, 300) containing the integrated circuit memory die and a second integrated circuit memory die, the address buffer to send the row and column addresses to the integrated circuit memory die and the second integrated circuit memory die.

### Claim 19 (depends on 16)

A memory as defined in claim 16, wherein the first ones of the bitlines activate a portion of the single one of the subarrays to access the cache line after receiving both row and column addresses associated with the cache line.

### Claim 20 (depends on 16)

A memory as defined in claim 16, wherein the integrated circuit memory die is a first die located on a memory module (200, 300) containing at least a second integrated circuit memory die, the second integrated circuit memory die in communication with the data interface, the first integrated circuit memory die to be activated without activating the second integrated circuit memory die when an address is received at the memory module to retrieve the entire cache line from the first integrated circuit memory die.

### Claim 21 (depends on 16)

A memory as defined in claim 16, wherein the integrated circuit memory die is located on a memory module (200, 300) containing the data interface, the data interface of the memory module having a larger bit length than a second data interface of the integrated circuit memory die, the readout of the entire cache line from the memory module to be performed using a burst size based on the bit length of the second data interface of the integrated circuit memory die.

### Claim 22 (depends on 16)

A memory as defined in claim 16, wherein the integrated circuit memory die is located on a memory module (200, 300) containing at least a second integrated circuit memory die in communication with the data interface, the integrated circuit memory die to output the cache line via the data interface while the second integrated circuit memory die concurrently outputs a second cache line via the data interface.

### Claim 23 (depends on 16)

A memory as defined in claim 16, wherein the integrated circuit memory die is to pre-charge the first bank after the first bitlines close the single one of the subarray, the pre-charge of the first bank to facilitate faster access to the first bank during a subsequent access of the first bank.

### Claim 24 (depends on 16)

A memory as defined in claim 16, wherein the data interface is in communication with a memory controller (102), the memory controller including a separate data queue for each bank of the integrated circuit memory die.

### Claim 25

A memory module, comprising:
a first memory (806g) having a first subarray (810a);
a second memory (806a) having a second subarray;
first bitlines (812) in the first memory to enable access to an entire first cache line in the first subarray; and
second bitlines in the second memory to enable access to an entire second cache line in the second subarray.

### Claim 26 (depends on 25)

A memory module as defined in claim 25, further comprising an address buffer (910, 1010, 1106) to latch row and column addresses received from a memory controller (102) to facilitate concurrently decoding the row and column addresses to activate the entire first cache line for reading out from the first subarray.

### Claim 27 (depends on 26)

A memory module as defined in claim 26, wherein the address buffer is external to the first and second memories and located on a memory module (200, 300) containing the first and second memories, the address buffer to send the row and column addresses to the first and second memories.

### Claim 28 (depends on 25)

A memory module as defined in claim 25, wherein the first bitlines activate a portion of the first subarray to access the first cache line after receiving both row and column addresses associated with the cache line.

### Claim 29 (depends on 25)

A memory module as defined in claim 25, wherein the first memory is to be activated to access the first cache line without activating the second memory, and the second memory is to be activated to access the second cache line without activating the first memory.

### Claim 30 (depends on 25)

A memory module as defined in claim 25, wherein the first and second memories are both in communication with a data interface (902), the first memory to output the first cache line via the data interface while the second memory is to concurrently output the second cache line via the data interface.

### Claim 31

A memory, comprising:
a plurality of memory chips (1702a, 1702i); and
a plurality of data storage locations and parity storage locations in each memory chip, each of the data storage locations to store a respective cache line (1704) and a corresponding checksum (1706), and each parity storage location to store a parity value (1708) for a corresponding subset of the data storage locations, the cache lines of a subset of the storage locations being stored in different memory chips.

### Claim 32 (depends on 31)

A memory as defined in claim 31, wherein upon an occurrence of an error in at least one of the data storage locations exposed by the checksum, an uncorrupted instance of the least one of the data storage locations is reconstructable based on the parity value.

### Claim 33 (depends on 32)

A memory as defined in claim 32, wherein the uncorrupted instance of the least one of the data storage locations is reconstructable using a reconstruction technique selected from a redundant array of inexpensive disks (RAID)-4 data reconstruction process or a RAID-5 data reconstruction process.

### Claim 34 (depends on 31)

A memory as defined in claim 31, wherein a first one of the memory chips is to service a read request by outputting a requested cache line and using an additional burst in a same read cycle to output a checksum corresponding to the requested cache line.

### Claim 35 (depends on 34)

A memory as defined in claim 34, wherein the checksum is stored in the first memory chip in association with the requested cache line.

### Claim 36 (depends on 31)

A memory as defined in claim 31, wherein a first one of the memory chips is to service a write request by storing a new cache line and its corresponding checksum to a first one of the memory chips.

### Claim 37 (depends on 36)

A memory as defined in claim 36, wherein the first memory chip is to further service the write request by storing a corresponding parity value associated with the second cache line.

### Claim 38 (depends on 36)

A memory as defined in claim 36, wherein to service the write request, the memory chip outputs an old cache line and a corresponding old checksum to a memory controller (802) prior to receiving the second cache line and the corresponding second checksum from the memory controller to replace the old cache line and the corresponding old checksum.

### Claim 39

A memory controller, comprising:
a data interface (1312a) to be in communication with a plurality of memory chips (1702a, 1702i) and exchange information with a plurality of data storage locations and parity storage locations in the at least one memory chip, the data interface to access a first cache line (1704) and a corresponding first checksum (1706) from a first subset of the data storage locations, and the data interface to access parity values (1708) for a corresponding subset of the data storage locations; and
a checksum generator (1318) to generate the first checksum for storing in association with the first cache line.

### Claim 40 (depends on 39)

A memory controller as defined in claim 39, further comprising:
an error detector (1316) to detect an error in at least one of the data storage locations based on the first checksum; and
a data reconstructor (1322) to reconstruct an uncorrupted instance of the least one of the data storage locations based on the parity value.

### Claim 41 (depends on 40)

A memory controller as defined in claim 40, wherein the data reconstructor is to reconstruct the uncorrupted instance of the at least one of the data storage locations using a reconstruction technique selected from a redundant array of inexpensive disks (RAID)-4 data reconstruction process or a RAID-5 data reconstruction process.

### Claim 42 (depends on 39)

A memory controller as defined in claim 39, wherein the data interface is to perform a read operation in a read cycle by reading a requested cache line from at least one of the memory chips and by initiating an additional burst in the same read cycle to read a checksum corresponding to the requested cache line.

### Claim 43 (depends on 39)

A memory controller as defined in claim 39, further comprising a parity generator (1320), the data interface is to follow a write operation with a read operation of a cache line written using the write operation and a parity value corresponding to the written cache line, and the parity generator is to calculate a new parity value for the written cache line based on the parity value.

### Claim 44 (depends on 39)

A memory controller as defined in claim 39, wherein the data interface is to perform a write operation by writing a new cache line and its corresponding checksum to a first one of the memory chips.

### Claim 45 (depends on 44)

A memory controller as defined in claim 44, wherein to perform the write operation, the data interface is to read an old cache line and a corresponding old checksum from the at least one memory chip prior to writing the second cache line and the corresponding second checksum to the at least one memory chip to replace the old cache line and the corresponding old checksum.