# US 2014/0208149 A1 · Apparatus and method for dynamically aligned source synchronous receiver > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0208149 A1 - Document ID: US20140208149A1 - Status: Published application - Kind: A1 - Application number: 13/757,575 - Filed: 2013-02-01 - Published: 2014-07-24 - Earliest claimed: 2013-01-22 - Assignees: VIA Technologies, Inc. - Inventors: Vanessa S. Canac; James R. Lundberg - Web page: https://patentgrep.com/patent/US20140208149A1 ## CPC - G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories} - G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators} - G06F 13/3625: {using a time dependent access} - G06F 13/4068: {Electrical coupling} - G06F 13/4217: {with synchronous protocol} - G06F 13/4243: {with synchronous protocol} - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus including a synchronous lag receiver that receives one of a plurality of radially distributed strobes and a data bit, and that delays registering of the data bit by a propagation time. The synchronous lag receiver has a first plurality of matched inverters, a first mux, and a bit receiver. The first plurality of matched inverters generates successively delayed versions of the data bit. The first mux receives a value on a lag bus that indicates the propagation time, and selects one of the successively delayed versions of the data bit that corresponds to the value. The bit receiver receives the one of the successively delayed versions of the data bit and one of a plurality of radially distributed strobe signals, and registers the state of the one of the successively delayed versions of the data bit upon assertion of the one of a plurality of distributed strobe signals. ## Claims ### Claim 1 An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising: a synchronous lag receiver, configured to receive one of a plurality of radially distributed strobes and a data bit, and configured to delay registering of said data bit by a propagation time, said synchronous lag receiver comprising: a first plurality of matched inverters, configured to generate successively delayed versions of said data bit; a first mux, coupled to said first plurality of matched inverters, configured to receive a value on a lag bus that indicates said propagation time, and configured to select one of said successively delayed versions of said data bit that corresponds to said value; and a bit receiver, configured to receive said one of said successively delayed versions of said data bit and one of a plurality of radially distributed strobe signals, and configured to register the state of said one of said successively delayed versions of said data bit upon assertion of said one of a plurality of radially distributed strobe signals. ### Claim 2 (depends on 1) The apparatus as recited in claim 1, wherein said one of a plurality of radially distributed strobe signals corresponds to a strobe, and wherein said strobe and said data bit are received by a corresponding device within which the apparatus is disposed and are sourced by a transmitting device. ### Claim 3 (depends on 2) The apparatus as recited in claim 2, wherein said corresponding device comprises an x86-compatible microprocessor. ### Claim 4 (depends on 1) The apparatus as recited in claim 1, further comprising: a bit lag control element, configured to measure said propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and configured to generate said value on said lag bus, said bit lag control element comprising: delay lock control, configured to select one of a plurality of successively delayed versions of said first signal that coincides with said assertion of said second signal; and a gray encoder, configured to gray encode said propagation time to generate said value on said lag bus. ### Claim 5 (depends on 4) The apparatus as recited in claim 4, wherein said delay lock control selects said one of a plurality of successively delayed versions of said first signal by incrementing and decrementing bus states of select inputs on a second mux, and wherein said plurality of successively delayed versions of said first signal comprises inputs to said mux. ### Claim 6 (depends on 4) The apparatus as recited in claim 4, wherein said bit lag control element further comprises: a second plurality of matched inverters, and wherein said propagation time is expressed as a function of zero or more of said second plurality of matched inverters. ### Claim 7 (depends on 4) The apparatus as recited in claim 4, wherein said first plurality of matched inverters are replicas of said second plurality of matched inverters. ### Claim 8 An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising: a microprocessor, comprising: a synchronous lag receiver, configured to receive one of a plurality of radially distributed strobes and a data bit, and configured to delay registering of said data bit by a propagation time, said synchronous lag receiver comprising: a first plurality of matched inverters, configured to generate successively delayed versions of said data bit; a first mux, coupled to said first plurality of matched inverters, configured to receive a value on a lag bus that indicates said propagation time, and configured to select one of said successively delayed versions of said data bit that corresponds to said value; and a bit receiver, configured to receive said one of said successively delayed versions of said data bit and one of a plurality of radially distributed strobe signals, and configured to register the state of said one of said successively delayed versions of said data bit upon assertion of said one of a plurality of radially distributed strobe signals. ### Claim 9 (depends on 8) The apparatus as recited in claim 8, wherein said one of a plurality of radially distributed strobe signals corresponds to a strobe, and wherein said strobe and said data bit are received by a corresponding device within which the apparatus is disposed and are sourced by a transmitting device. ### Claim 10 (depends on 9) The apparatus as recited in claim 9, wherein said corresponding device comprises an x86-compatible microprocessor. ### Claim 11 (depends on 8) The apparatus as recited in claim 8, further comprising: a bit lag control element, configured to measure said propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and configured to generate said value on said lag bus, said bit lag control element comprising: delay lock control, configured to select one of a plurality of successively delayed versions of said first signal that coincides with said assertion of said second signal; and a gray encoder, configured to gray encode said propagation time to generate said value on said lag bus. ### Claim 12 (depends on 11) The apparatus as recited in claim 11, wherein said delay lock control selects said one of a plurality of successively delayed versions of said first signal by incrementing and decrementing bus states of select inputs on a second mux, and wherein said plurality of successively delayed versions of said first signal comprises inputs to said mux. ### Claim 13 (depends on 11) The apparatus as recited in claim 11, wherein said bit lag control element further comprises: a second plurality of matched inverters, and wherein said propagation time is expressed as a function of zero or more of said second plurality of matched inverters. ### Claim 14 (depends on 4) The apparatus as recited in claim 4, wherein said first plurality of matched inverters are replicas of said second plurality of matched inverters. ### Claim 15 A method that compensates for misalignment on a synchronous data bus, the method comprising: first receiving one of a plurality of radially distributed strobes and a data bit, and delaying registering of the data bit by a propagation time, said first receiving comprising: first generating successively delayed versions of the data bit; second receiving a value on a lag bus that indicates the propagation time, and first selecting one of the successively delayed versions of the data bit that corresponds to said value; and registering the state of the one of said successively delayed versions of the data bit upon assertion of one of a plurality of radially distributed strobe signals. ### Claim 16 (depends on 15) The method as recited in claim 15, wherein the one of a plurality of radially distributed strobes signals corresponds to a strobe, and wherein the strobe and the data bit are received by a corresponding device within which the apparatus is disposed and are sourced by a transmitting device. ### Claim 17 (depends on 16) The method as recited in claim 16, wherein the corresponding device comprises an x86-compatible microprocessor. ### Claim 18 (depends on 15) The method as recited in claim 15, further comprising: measuring the propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and second generating the value on the lag bus, said measuring comprising: second selecting one of a plurality of successively delayed versions of the first signal that coincides with the assertion of the second signal; and gray encoding the propagation time to generate the value on the lag bus. ### Claim 19 (depends on 18) The method as recited in claim 18, wherein said second selecting comprises: incrementing and decrementing bus states of select inputs on a mux, wherein the plurality of successively delayed versions of the first signal comprises inputs to the mux. ### Claim 20 (depends on 18) The method as recited in claim 18, wherein said measuring further comprises: expressing the propagation time as a function of zero or more of a first plurality of matched inverters.