# US 2014/0208148 A1 · Automatic source synchronous bus signal alignment compensation mechanism

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0208148 A1
- Document ID: US20140208148A1
- Status: Published application
- Kind: A1
- Application number: 13/757,480
- Filed: 2013-02-01
- Published: 2014-07-24
- Earliest claimed: 2013-01-22
- Assignees: VIA Technologies, Inc.
- Inventors: Vanessa S. Canac; James R. Lundberg
- Web page: https://patentgrep.com/patent/US20140208148A1

## CPC

- G06F 13/4243: {with synchronous protocol}
- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G06F 13/4217: {with synchronous protocol}
- G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories}
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An apparatus including a Joint Test Action Group (JTAG) interface and a bit lag control element. The JTAG interface receives information that indicates an amount to adjust a propagation time. The bit lag control element measures the propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and generates a value indicating an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value indicating the propagation time. The adjust logic adjusts the second value by the amount prescribed by the JTAG interface to yield a third value. The gray encoder gray encodes the third value to generate the value on the lag bus.

## Claims

### Claim 1

An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising:
a Joint Test Action Group (JTAG) interface, configured to receive control information over a standard JTAG bus, wherein said control information indicates an amount to adjust a propagation time; and
a bit lag control element, configured to measure said propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and configured to generate a first value on a lag bus that indicates an adjusted propagation time, said bit lag control element comprising:
delay lock control, configured to select one of a plurality of successively delayed versions of said first signal that coincides with said assertion said second signal, and configured to generate a second value on a lag select bus that indicates said propagation time;
adjust logic, coupled to said JTAG interface and to said lag select bus, configured adjust said second value by said amount prescribed by said JTAG interface to yield a third value that is output to an adjusted lag bus; and
a gray encoder, configured to gray encode said third value to generate said first value on said lag bus.

### Claim 2 (depends on 1)

The apparatus as recited in claim 1, wherein said delay lock control selects said one of a plurality of successively delayed versions of said first signal by incrementing and decrementing bus states of select inputs on a mux, and wherein said plurality of successively delayed versions comprises inputs to said mux.

### Claim 3 (depends on 2)

The apparatus as recited in claim 2, wherein said bit lag control element further comprises:
a first plurality of matched inverters, wherein said propagation time is expressed as a function of zero or more of said first plurality of matched inverters.

### Claim 4 (depends on 3)

The apparatus as recited in claim 3, further comprising:
a synchronous lag receiver, coupled to said bit lag control element, configured to receive one of a plurality of radially distributed strobes and a data bit, and configured to delay registering of said data bit by said adjusted propagation time.

### Claim 5 (depends on 4)

The apparatus as recited in claim 4, wherein said one of a plurality of radially distributed strobes corresponds to a strobe, and wherein said strobe and said data bit are received by a corresponding device within which the apparatus is disposed and are sourced by a transmitting device.

### Claim 6 (depends on 4)

The apparatus as recited in claim 4, wherein said synchronous lag receiver comprises a second plurality of matched inverters that are replicas of said first plurality of matched inverters.

### Claim 7 (depends on 6)

The apparatus as recited in claim 6, wherein said synchronous lag receiver delays registering of said data bit by propagating said data bit through zero or more of said second plurality of matched inverters as indicated by said value.

### Claim 8

An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising:
a microprocessor, comprising:
a Joint Test Action Group (JTAG) interface, configured to receive control information over a standard JTAG bus, wherein said control information indicates an amount to adjust a propagation time; and
a bit lag control element, configured to measure said propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and configured to generate a first value on a lag bus that indicates an adjusted propagation time, said bit lag control element comprising:
delay lock control, configured to select one of a plurality of successively delayed versions of said first signal that coincides with said assertion said second signal, and configured to generate a second value on a lag select bus that indicates said propagation time;
adjust logic, coupled to said JTAG interface and to said lag select bus, configured adjust said second value by said amount prescribed by said JTAG interface to yield a third value that is output to an adjusted lag bus; and
a gray encoder, configured to gray encode said third value to generate said first value on said lag bus.

### Claim 9 (depends on 8)

The apparatus as recited in claim 8, wherein said delay lock control selects said one of a plurality of successively delayed versions of said first signal by incrementing and decrementing bus states of select inputs on a mux, and wherein said plurality of successively delayed versions comprises inputs to said mux.

### Claim 10 (depends on 9)

The apparatus as recited in claim 9, wherein said bit lag control element further comprises:
a first plurality of matched inverters, wherein said propagation time is expressed as a function of zero or more of said first plurality of matched inverters.

### Claim 11 (depends on 10)

The apparatus as recited in claim 10, wherein said microprocessor further comprises:
a synchronous lag receiver, coupled to said bit lag control element, configured to receive one of a plurality of radially distributed strobes and a data bit, and configured to delay registering of said data bit by said adjusted propagation time.

### Claim 12 (depends on 11)

The apparatus as recited in claim 11, wherein said one of a plurality of radially distributed strobes corresponds to a strobe, and wherein said strobe and said data bit are received by a corresponding device within which the apparatus is disposed and are sourced by a transmitting device.

### Claim 13 (depends on 11)

The apparatus as recited in claim 11, wherein said synchronous lag receiver comprises a second plurality of matched inverters that are replicas of said first plurality of matched inverters.

### Claim 14 (depends on 13)

The apparatus as recited in claim 13, wherein said synchronous lag receiver delays registering of said data bit by propagating said data bit through zero or more of said second plurality of matched inverters as indicated by said value.

### Claim 15

A method that compensates for misalignment on a synchronous data bus, the method comprising:
receiving control information over a standard JTAG bus, wherein the control information indicates an amount to adjust a propagation time; and
measuring the propagation time beginning with assertion of a first signal and ending with assertion of a second signal, said measuring comprising:
selecting one of a plurality of successively delayed versions of the first signal that coincides with assertion of the second signal;
adjusting the propagation time by the amount prescribed by the control information to yield an adjusted propagation time; and
gray encoding the adjusted propagation time to generate a value on a lag bus.

### Claim 16 (depends on 15)

The method as recited in claim 15, wherein said selecting one of a plurality of successively delayed versions of the first signal comprises:
incrementing and decrementing bus states of select inputs on a mux, wherein the plurality of successively delayed versions comprises inputs to the mux.

### Claim 17 (depends on 16)

The method as recited in claim 16, wherein said measuring further comprises:
expressing the propagation time as a function of zero or more of a first plurality of matched inverters.

### Claim 18 (depends on 17)

The method as recited in claim 17, further comprising:
coupling the lag bus to a synchronous lag receiver, configured to receive one of a plurality of radially distributed strobes and a data bit, and configured to delay registering of the data bit by the adjusted propagation time.

### Claim 19 (depends on 18)

The method as recited in claim 18, wherein the one of a plurality of radially distributed strobes corresponds to a strobe, and wherein the strobe and the data bit are received by a corresponding device and are sourced by a transmitting device.

### Claim 20 (depends on 18)

The method as recited in claim 18, wherein the synchronous lag receiver comprises a second plurality of matched inverters that are replicas of the first plurality of matched inverters.

### Claim 21 (depends on 20)

The method as recited in claim 20, wherein the synchronous lag receiver delays registering of the data bit by propagating the data bit through zero or more of the second plurality of matched inverters as indicated by the value.