# US 2014/0208144 A1 · Method and Apparatus for Adaptive Power Management of Memory Subsystem

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- Number: US 2014/0208144 A1
- Document ID: US20140208144A1
- Status: Published application
- Kind: A1
- Application number: 13/748,299
- Filed: 2013-01-23
- Published: 2014-07-24
- Earliest claimed: 2013-01-23
- Assignees: Broadcom Corporation
- Applicants: Broadcom Corporation
- Inventors: Kenneth MA
- Web page: https://patentgrep.com/patent/US20140208144A1

## CPC

- G06F 1/3287: by switching off individual functional units in the computer system
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A method and apparatus are disclosed for performing adaptive memory power management in a system employing a CPU and a memory subsystem. A CPU throttle control (THR) module generates a CPU throttle control signal indicating when the CPU is idle. A memory controller (MC) module generates memory power management signals based on at least one of the CPU throttle control signal, memory read/write signals, memory access break events, and bus master access requests. Certain portions of the memory subsystem are powered down in response to the memory power management signals. Memory power management is performed on a time segment by time segment basis to achieve efficient power management of the memory subsystem during CPU run time.

## Claims

### Claim 1

In a system comprising a CPU and a memory, a method for performing adaptive power management of said memory, said method comprising:
detecting pending read/write cycles from the CPU;
storing memory access information based on the detected pending read/write cycles; and
controlling the power state of the memory according to the stored access information.

### Claim 2 (depends on 1)

The method of claim 1, further comprising decoding the stored memory access information to determine portions of the memory to be accessed.

### Claim 3 (depends on 2)

The method of claim 2, wherein the controlling controls the power state of the memory based on the determined portions of the memory to be accessed.

### Claim 4 (depends on 3)

The method of claim 3, wherein the controlling powers down all portions of the memory other than the determined portions of the memory to be accessed.

### Claim 5 (depends on 1)

The method of claim 1, further comprising predicting portions of the memory to be accessed based on the stored memory access information.

### Claim 6 (depends on 5)

The method of claim 5, wherein the controlling controls the memory to power down all portions of the memory other than the predicted portions of the memory to be accessed.

### Claim 7 (depends on 6)

The method of claim 6, wherein the controlling controls the memory to maintain the predicted portions to be accessed in a powered state until accessed, and controls the memory to power down the predicted portions to be accessed once accessed.

### Claim 8

A system comprising a CPU and a memory, comprising:
a read write buffer controller configured to detect pending read/write cycles from the CPU, and configured to store memory access information based on the detected pending read/write cycles; and
a controller configured to control the power state of the memory according to the stored access information.

### Claim 9 (depends on 8)

The method of claim 8, wherein the read/write buffer controller is further configured to decode the stored memory access information to determine portions of the memory to be accessed.

### Claim 10 (depends on 9)

The method of claim 9, wherein the controller controls the power state of the memory based on the determined portions of the memory to be accessed.

### Claim 11 (depends on 10)

The method of claim 10, wherein the controller powers down all portions of the memory other than the determined portions of the memory to be accessed.

### Claim 12 (depends on 8)

The method of claim 8, wherein the read/write buffer controller is further configured to predict portions of the memory to be accessed based on the stored memory access information.

### Claim 13 (depends on 12)

The method of claim 12, wherein the controller controls the memory to power down all portions of the memory other than the predicted portions portion of the memory to be accessed.

### Claim 14 (depends on 13)

The method of claim 13, wherein the controller controls the memory to maintain the predicted portions to be accessed in a powered state until accessed, and controls the memory to power down the predicted portions to be accessed once accessed.

### Claim 15

In a system comprising a CPU and a memory, a method for performing adaptive power management of said memory, said method comprising:
storing memory access information in memory based on detected memory activity;
monitoring an activity level of the CPU; and
controlling the power state of the memory according to the stored access information and the activity level of the CPU.

### Claim 16 (depends on 15)

The method of claim 15, wherein the memory access information identifies requests for access to portions the memory by component devices.

### Claim 17 (depends on 16)

The method of claim 16, wherein the controlling controls the memory to be in a powered state when the CPU has a high activity level.

### Claim 18 (depends on 17)

The method of claim 17, wherein the controlling controls the memory to be in a powered-down state when the CPU has a low activity level and the memory access information identifies no requests for access.

### Claim 19 (depends on 18)

The method of claim 18, wherein the controlling controls first portions of the memory to be in a powered state and second portions of the memory to be in a powered-down state when the CPU has a low activity level and the memory access information identifies requests for access to the first portions of the memory.

### Claim 20 (depends on 17)

The method of claim 17, wherein the low activity level of the CPU represents any of a stop grant state, a stop clock state, and a deep sleep state.