# US 2014/0208109 A1 · Method and system for protecting memory information in a platform

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- Number: US 2014/0208109 A1
- Document ID: US20140208109A1
- Status: Published application
- Kind: A1
- Application number: 13/976,935
- Filed: 2011-12-28
- Published: 2014-07-24
- Earliest claimed: 2011-12-28
- Assignees: Intel Corporation
- Inventors: Alpa T. Narendra Trivedi; David M. Durham; Men Long; Siddhartha Chhabra; Uday R. Savagaonkar; Carlos V. Rozas
- Web page: https://patentgrep.com/patent/US20140208109A1

## CPC

- G06F 21/64: Protecting data integrity, e.g. using checksums, certificates or signatures
- G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)}
- G06F 21/78: to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00)
- G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories
- H04L 9/0643: {Hash functions, e.g. MD5, SHA, HMAC or f9 MAC}
- H04L 2209/12: Details relating to cryptographic hardware or logic circuitry
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A method and system to provide an effective, scalable and yet low-cost solution for Confidentiality, Integrity and Replay protection for sensitive information stored in a memory and prevent an attacker from observing and/or modifying the state of the system. In one embodiment of the invention, the system has strong hardware protection for its memory contents via XTS-tweak mode of encryption where the tweak is derived based on “Global and Local Counters”. This scheme offers to enable die-area efficient Replay protection for any sized memory by allowing multiple counter levels and facilitates using small counter-sizes to derive the “tweak” used in the XTS encryption without sacrificing cryptographic strength.

## Claims

### Claim 1

A processor comprising:
a global counter;
a plurality of local counters, wherein a last level of the plurality of local counters is associated with a plurality of Message Authentication Code (MAC) lines; and
logic to perform a write operation to a memory address, wherein the logic is to decrypt one of the MAC lines associated with the memory address using a tweak based on one or more of the memory address, the global counter, the local counter associated with the one MAC line, and a counter indication bit to obtain a MAC value.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the logic to perform the write operation to the memory address is further to:
determine whether an address of the local counter associated with the one MAC line is greater than a counter index;
assert the counter indication bit in response to a determination that the address of the local counter associated with the one MAC line is lesser than the counter index; and
de-assert the counter indication bit in response to a determination that the address of the local counter associated with the one MAC line is greater than the counter index.

### Claim 3 (depends on 2)

The processor of claim 2, wherein the logic to perform the write operation to the memory address is further to:
write data to the memory address; and
update the one MAC line associated with the memory address with the MAC value.

### Claim 4 (depends on 3)

The processor of claim 3, wherein the logic to perform the write operation to the memory address is further to:
determine whether an update interval has been reached;
if so,
reset one of the plurality of local counters associated with the current counter; and
increment the counter index by one; and
if not so,
increment the local counter associated with the one MAC line by one.

### Claim 5 (depends on 4)

The processor of claim 4, wherein the logic to perform the write operation to the memory address is further to:
determine another tweak based on one or more of the memory address, the global counter, the local counter associated with the one MAC line, and the counter indication bit; and
encrypt the one MAC line associated with the memory address using the other tweak.

### Claim 6 (depends on 1)

The processor of claim 1, wherein the logic is further to:
determine whether the counter index is set to its maximum value; and
in response to a determination that the counter index is set to its maximum value, increment the global counter by one; and
set the counter index to zero.

### Claim 7 (depends on 1)

The processor of claim 1, wherein the logic is further to perform a read operation to the memory address, wherein the logic is to decrypt the one MAC line associated with the memory address using the tweak to obtain the MAC value.

### Claim 8 (depends on 7)

The processor of claim 7, wherein the logic to perform the read operation to the memory address is further to:
determine whether an address of the local counter associated with the one MAC line is greater than a counter index;
assert the counter indication bit in response to a determination that the address of the local counter associated with the one MAC line is lesser than the counter index; and
de-assert the counter indication bit in response to a determination that the address of the local counter associated with the one MAC line is greater than the counter index.

### Claim 9 (depends on 8)

The processor of claim 8, wherein the logic to perform the read operation to the memory address is further to:
authenticate a data line associated with the memory address using the MAC value; and
read contents of the data line in response to a successful authentication of the data line associated with the memory address using the MAC value.

### Claim 10

A system comprising:
a memory; and
a processor coupled with the memory, the processing comprising:
a global counter;
a plurality of local counters, wherein a last level of the plurality of local counters is associated with a plurality of Message Authentication Code (MAC) lines; and
logic to perform a write operation to a memory address, wherein the logic is to decrypt one of the MAC lines associated with the memory address using a tweak based on one or more of the memory address, the global counter, the local counter associated with the one MAC line, and a counter indication bit to obtain a MAC value.

### Claim 11 (depends on 10)

The system of claim 10, wherein the logic to perform the write operation to the memory address is further to:
determine whether an address of the local counter associated with the one MAC line is greater than a counter index;
assert the counter indication bit in response to a determination that the address of the local counter associated with the one MAC line is lesser than the counter index; and
de-assert the counter indication bit in response to a determination that the address of the local counter associated with the one MAC line is greater than the counter index.

### Claim 12 (depends on 11)

The system of claim 11, wherein the logic to perform the write operation to the memory address is further to:
write data to the memory address; and
update the one MAC line associated with the memory address with the MAC value.

### Claim 13 (depends on 12)

The system of claim 12, wherein the logic to perform the write operation to the memory address is further to:
determine whether an update interval has been reached;
if so,
reset one of the plurality of local counters associated with the current counter; and
increment the counter index by one; and
if not so,
increment the local counter associated with the one MAC line by one.

### Claim 14 (depends on 13)

The system of claim 13, wherein the logic to perform the write operation to the memory address is further to:
determine another tweak based on one or more of the memory address, the global counter, the local counter associated with the one MAC line, and the counter indication bit; and
encrypt the one MAC line associated with the memory address using the other tweak.

### Claim 15 (depends on 10)

The system of claim 10, wherein the logic is further to:
determine whether the counter index is set to its maximum value; and
in response to a determination that the counter index is set to its maximum value, increment the global counter by one; and
set the counter index to zero.

### Claim 16 (depends on 10)

The system of claim 10, wherein the logic is further to perform a read operation to the memory address, wherein the logic is to decrypt the one MAC line associated with the memory address using the tweak to obtain the MAC value.

### Claim 17 (depends on 16)

The system of claim 16, wherein the logic to perform the read operation to the memory address is further to:
determine whether an address of the local counter associated with the one MAC line is greater than a counter index;
assert the counter indication bit in response to a determination that the address of the local counter associated with the one MAC line is lesser than the counter index; and
de-assert the counter indication bit in response to a determination that the address of the local counter associated with the one MAC line is greater than the counter index.

### Claim 18 (depends on 16)

The system of claim 16, wherein the logic to perform the read operation to the memory address is further to:
authenticate a data line associated with the memory address using the MAC value; and
read contents of the data line in response to a successful authentication of the data line associated with the memory address using the MAC value.

### Claim 19

A method comprising:
performing a write operation to a memory address, wherein performing the write operation comprises decrypting one of a plurality of the Message Authentication Code (MAC) lines associated with the memory address using a tweak based on one or more of the memory address, a global counter, a local counter associated with the one MAC line, and a counter indication bit to obtain a MAC value.

### Claim 20 (depends on 19)

The method of claim 19, wherein performing the write operation comprises:
determining whether an address of the local counter associated with the one MAC line is greater than a counter index;
asserting the counter indication bit in response to a determination that the address of the local counter associated with the one MAC line is lesser than the counter index; and
de-asserting the counter indication bit in response to a determination that the address of the local counter associated with the one MAC line is greater than the counter index.

### Claim 21 (depends on 20)

The method of claim 20, wherein performing the write operation comprises:
writing data to the memory address; and
updating the one MAC line associated with the memory address with the MAC value.

### Claim 22 (depends on 21)

The method of claim 21, wherein performing the write operation comprises:
determining whether an update interval has been reached;
if so,
resetting one of the plurality of local counters associated with the current counter; and
incrementing the counter index by one; and
if not so,
incrementing the local counter associated with the one MAC line by one.

### Claim 23 (depends on 19)

The method of claim 19, wherein performing the write operation comprises:
determining another tweak based on one or more of the memory address, the global counter, the local counter associated with the one MAC line, and the counter indication bit; and
encrypting the one MAC line associated with the memory address using the other tweak.

### Claim 24 (depends on 19)

The method of claim 19, wherein performing the write operation comprises:
determining whether the counter index is set to its maximum value; and
in response to a determination that the counter index is set to its maximum value, incrementing the global counter by one; and
setting the counter index to zero.

### Claim 25 (depends on 19)

The method of claim 19, further comprising:
performing a read operation to the memory address, wherein performing the read operation comprises decrypting the one MAC line associated with the memory address using the tweak to obtain the MAC value.

### Claim 26 (depends on 25)

The method of claim 25, wherein performing the read operation further comprises:
determining whether an address of the local counter associated with the one MAC line is greater than a counter index;
asserting the counter indication bit in response to a determination that the address of the local counter associated with the one MAC line is lesser than the counter index; and
de-asserting the counter indication bit in response to a determination that the address of the local counter associated with the one MAC line is greater than the counter index.

### Claim 27 (depends on 26)

The method of claim 26, wherein performing the read operation further comprises:
authenticating a data line associated with the memory address using the MAC value; and
reading contents of the data line in response to a successful authentication of the data line associated with the memory address using the MAC value.