# US 2014/0208086 A1 · Vector exception code > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0208086 A1 - Document ID: US20140208086A1 - Status: Published application - Kind: A1 - Application number: 13/748,504 - Filed: 2013-01-23 - Published: 2014-07-24 - Earliest claimed: 2013-01-23 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Jonathan D. Bradbury; Michael K. Gschwind; Eric M. Schwarz; Timothy J. Slegel - Web page: https://patentgrep.com/patent/US20140208086A1 ## CPC - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/30098: {Register arrangements} - G06F 9/323: {for indirect branch instructions} - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The vector exception code also includes a reason for the exception. ## Claims ### Claim 1 A computer program product for facilitating exception handling, the computer program product comprising: a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: determining, by a processor, that an instruction executing within a computing environment has caused an exception, the instruction to operate on a vector register comprising a plurality of elements; and obtaining, based on the exception, a vector exception code, the vector exception code including a position of an element of the plurality of elements of the vector register that caused the exception. ### Claim 2 (depends on 1) The computer program product of claim 1, wherein the position comprises an index within the vector register corresponding to the element that caused the exception. ### Claim 3 (depends on 1) The computer program product of claim 1, wherein the position comprises a lowest indexed element in the vector register which caused the exception. ### Claim 4 (depends on 1) The computer program product of claim 1, wherein the obtaining is based on the exception causing an interrupt. ### Claim 5 (depends on 1) The computer program product of claim 1, wherein the vector exception code comprises a first portion to specify the position, and a second portion to specify a vector interrupt code. ### Claim 6 (depends on 5) The computer program product of claim 5, wherein the position comprises a lowest indexed element in the vector register which caused the exception. ### Claim 7 (depends on 5) The computer program product of claim 5, wherein the vector interrupt code comprises a value to indicate one of an invalid operation, division by zero, an overflow, an underflow or an inexact result. ### Claim 8 (depends on 1) The computer program product of claim 1, wherein the method further comprises determining which one or more elements of the vector register caused the exception, and obtaining, based on the determining which one or more elements caused the exception, the position to be included in the vector exception code. ### Claim 9 (depends on 8) The computer program product of claim 8, wherein the obtaining the position comprising determining the lowest indexed element of the one or more elements that caused the exception and using an index of the lowest indexed element as the position. ### Claim 10 A computer system for facilitating exception handling, the computer system comprising: a memory; and a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising: determining, by a processor, that an instruction executing within a computing environment has caused an exception, the instruction to operate on a vector register comprising a plurality of elements; and obtaining, based on the exception, a vector exception code, the vector exception code including a position of an element of the plurality of elements of the vector register that caused the exception. ### Claim 11 (depends on 10) The computer system of claim 10, wherein the position comprises an index within the vector register corresponding to the element which caused the exception. ### Claim 12 (depends on 10) The computer system of claim 10, wherein the vector exception code comprises a first portion to specify the position, and a second portion to specify a vector interrupt code. ### Claim 13 (depends on 12) The computer system of claim 12, wherein the position comprises an index within the vector register corresponding to the element which caused the exception. ### Claim 14 (depends on 12) The computer system of claim 12, wherein the vector interrupt code comprises a value to indicate one of an invalid operation, division by zero, an overflow, an underflow or an inexact result. ### Claim 15 (depends on 10) The computer system of claim 10, wherein the method further comprises determining which one or more elements of the vector register caused the exception, and obtaining, based on the determining which one or more elements caused the exception, the position to be included in the vector exception code, and wherein the obtaining the position comprising determining the lowest indexed element of the one or more elements that caused the exception and using an index of the lowest indexed element as the position. ### Claim 16 A method of facilitating exception handling, the method comprising: determining, by a processor, that an instruction executing within a computing environment has caused an exception, the instruction to operate on a vector register comprising a plurality of elements; and obtaining, based on the exception, a vector exception code, the vector exception code including a position of an element of the plurality of elements of the vector register that caused the exception. ### Claim 17 (depends on 16) The method of claim 16, wherein the position comprises a lowest indexed element in the vector register which caused the exception. ### Claim 18 (depends on 16) The method of claim 16, wherein the vector exception code comprises a first portion to specify the position, and a second portion to specify a vector interrupt code. ### Claim 19 (depends on 18) The method of claim 18, wherein the vector interrupt code comprises a value to indicate one of an invalid operation, division by zero, an overflow, an underflow or an inexact result. ### Claim 20 (depends on 16) The method of claim 16, further comprising determining which one or more elements of the vector register caused the exception, and obtaining, based on the determining which one or more elements caused the exception, the position to be included in the vector exception code, and wherein the obtaining the position comprising determining the lowest indexed element of the one or more elements that caused the exception and using an index of the lowest indexed element as the position.