# US 2014/0208084 A1 · Compound complex instruction set computer (ccisc) processor architecture

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- Number: US 2014/0208084 A1
- Document ID: US20140208084A1
- Status: Published application
- Kind: A1
- Application number: 13/746,239
- Filed: 2013-01-21
- Published: 2014-07-24
- Earliest claimed: 2013-01-21
- Inventors: Tom Yap
- Web page: https://patentgrep.com/patent/US20140208084A1

## CPC

- G06F 9/30: Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22)
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/30167: {of immediate specifier, e.g. constants}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processor system includes a multichannel memory operable to store data values and a program memory operable to store Compound CISC (CCISC) instructions. The processor system also includes a processor operable to execute a computer program assembled with at least a portion of the compound CCISC instructions, to retrieve a CCISC instruction from the program memory, to access at least two data values in the multichannel memory based on the executed computer program, and to operate on the at least two data values in the multichannel memory based on the C-CISC instruction. The processor retrieves the CCISC instruction, accesses the at least two data values, and operates on the at least two data values during a same clock cycle.

## Claims

### Claim 1

A processor system, comprising:
a multichannel memory operable to store data values;
a program memory operable to store Compound CISC (CCISC) instructions; and
a processor operable to execute a computer program assembled with at least a portion of the compound CCISC instructions, to retrieve a CCISC instruction from the program memory, to access at least two data values in the multichannel memory based on the executed computer program, and to operate on the at least two data values in the multichannel memory based on the C-CISC instruction,
wherein the processor retrieves the CCISC instruction, accesses the at least two data values, and operates on the at least two data values during a same clock cycle.

### Claim 2 (depends on 1)

The processor system of claim 1, wherein:
the processor, in operating on the at least two data values, is operable to compare the at least two data values to branch to an address in the program memory.

### Claim 3 (depends on 1)

The processor system of claim 1, wherein:
the processor, in operating on the at least two data values, is operable to change at least one of the data values in the multichannel memory.

### Claim 4 (depends on 1)

The processor system of claim 1, wherein:
the processor, in operating on the at least to data values, is operable to move at least one data value from a first address to a second address in the multichannel memory based on the C-CISC instruction.

### Claim 5 (depends on 1)

The processor system of claim 1, wherein:
the processor is an 8-bit processor.

### Claim 6 (depends on 1)

The processor system of claim 1, further comprising:
an address generation unit operable to generate addresses to access the at least two data values in the multichannel memory.

### Claim 7

A method, comprising:
initiating execution of a program;
storing data values in a multichannel memory based on the program; and
during a same clock cycle:
retrieving a Compound CISC (CCISC) instruction from a program memory based on the program;
accessing the at least two data values in the multichannel memory based on the computer program; and
operating on the at least two data values in the multichannel memory based on the C-CISC instruction.

### Claim 8 (depends on 7)

The method of claim 7, wherein:
in operating on the at least two data values, the method further comprises comparing the at least two data values to branch to an address in the program memory.

### Claim 9 (depends on 7)

The method of claim 7, wherein:
in operating on the at least two data values, the method further comprises changing at least one of the data values in the multichannel memory.

### Claim 10 (depends on 7)

The method of claim 7, wherein:
in operating on the at least two data values, the method further comprises moving at least one data value from a first address to a second address in the multichannel memory based on the C-CISC instruction.

### Claim 11 (depends on 7)

The method of claim 7, further comprising:
processing CCISC instruction with an 8-bit processor.

### Claim 12 (depends on 7)

The method of claim 7, wherein:
accessing the at least two data values in the multichannel memory comprises generating addresses with an address generation unit to access the at least two data values in the multichannel memory.

### Claim 13

A non-transitory computer readable medium embodying programmed instructions which, when executed by processor, direct the processor to:
initiate execution of a program;
store data values in a multichannel memory based on the program; and
during a same clock cycle:
retrieve a Compound CISC (CCISC) instruction from a program memory based on the program;
access the at least two data values in the multichannel memory based on the computer program; and
operate on the at least two data values in the multichannel memory based on the C-CISC instruction.

### Claim 14 (depends on 13)

The medium of claim 13, wherein:
in operating on the at least two data values, the instructions direct the processor to compare the at least two data values to branch to an address in the program memory.

### Claim 15 (depends on 13)

The medium of claim 13, wherein:
in operating on the at least two data values, the instructions direct the processor to change at least one of the data values in the multichannel memory.

### Claim 16 (depends on 13)

The medium of claim 13, wherein:
in operating on the at least two data values, the instructions direct the processor to move at least one data value from a first address to a second address in the multichannel memory based on the C-CISC instruction.

### Claim 17 (depends on 13)

The medium of claim 13, further comprising:
process CCISC instruction with an 8-bit processor.

### Claim 18 (depends on 13)

The medium of claim 13, wherein:
in accessing the at least two data values in the multichannel memory, the instructions further direct the processor to generate addresses with an address generation unit to access the at least two data values in the multichannel memory.