# US 2014/0208080 A1 · Apparatus and method for down conversion of data types > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0208080 A1 - Document ID: US20140208080A1 - Status: Published application - Kind: A1 - Application number: 13/997,006 - Filed: 2011-12-23 - Published: 2014-07-24 - Earliest claimed: 2011-12-23 - Assignees: Intel Corporation - Inventors: Elmoustapha Ould-Ahmed-Vall; Robert Valentine; Tal Uliel; Jesus Corbal; Zeev Sperber; Amit Gradstein - Web page: https://patentgrep.com/patent/US20140208080A1 ## CPC - G06F 9/30101: {Special purpose registers} - G06F 9/3001: {Arithmetic instructions} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus and method are described for down-converting from a source operand to a destination operand with masking. For example, a method according to one embodiment includes the following operations: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; if the mask register bit(s) indicates that a masking operation is to be performed, then performing a specified masking operation and storing the results of the masking operation in the destination location; and if the mask register bit(s) indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the specified destination location. ## Claims ### Claim 1 A processor to execute one or more instructions to perform the operations of: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; if the mask register bit(s) indicates that a masking operation is to be performed, then performing a specified masking operation and storing the results of the masking operation in the destination location; and if the mask register bit(s) indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the specified destination location. ### Claim 2 (depends on 1) The processor as in claim 1 wherein if the mask register bit(s) indicates that a masking operation is not to be performed, then determining whether to perform trunction or signed/unsigned saturation to generate the down-converted value and, based on the determination, performing trunction or signed/unsigned saturation to generate the down-converted value. ### Claim 3 (depends on 1) The processor as in claim 1 wherein the specified masking operation comprises setting the bits of the data element in the destination register all equal to zero. ### Claim 4 (depends on 1) The processor as in claim 1 wherein the specified masking operation comprises maintaining existing values previously stored in the data element in the destination location. ### Claim 5 (depends on 1) The processor as in claim 1 wherein the destination location comprises a destination register. ### Claim 6 (depends on 1) The processor as in claim 1 wherein the destination location comprises a memory. ### Claim 7 (depends on 1) The processor as in claim 1 wherein the source operand value comprises a 128-bit value and the down-converted value comprises an 8-bit value. ### Claim 8 A method comprising: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; if the mask register bit(s) indicates that a masking operation is to be performed, then performing a specified masking operation and storing the results of the masking operation in the destination location; and if the mask register bit(s) indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the specified destination location. ### Claim 9 (depends on 8) The method as in claim 8 wherein if the mask register bit(s) indicates that a masking operation is not to be performed, then determining whether to perform trunction or signed/unsigned saturation to generate the down-converted value and, based on the determination, performing trunction or signed/unsigned saturation to generate the down-converted value. ### Claim 10 (depends on 8) The method as in claim 8 wherein the specified masking operation comprises setting the bits of the data element in the destination register all equal to zero. ### Claim 11 (depends on 8) The method as in claim 8 wherein the specified masking operation comprises maintaining existing values previously stored in the data element in the destination location. ### Claim 12 (depends on 8) The method as in claim 8 wherein the destination location comprises a destination register. ### Claim 13 (depends on 6) The method as in claim 6 wherein the destination location comprises a memory. ### Claim 14 (depends on 8) The method as in claim 8 wherein the source operand value comprises a 128-bit value and the down-converted value comprises an 8-bit value. ### Claim 15 A processor comprising: means for reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; means for reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; means for performing a specified masking operation and storing the results of the masking operation in the destination location if the mask register bit(s) indicates that a masking operation is to be performed; and means for down-converting the source operand value and storing the down-converted value in the specified destination location if the mask register bit(s) indicates that a masking operation is not to be performed. ### Claim 16 (depends on 15) The processor as in claim 15 wherein if the mask register bit(s) indicates that a masking operation is not to be performed, then determining whether to perform trunction or signed/unsigned saturation to generate the down-converted value and, based on the determination, performing trunction or signed/unsigned saturation to generate the down-converted value. ### Claim 17 (depends on 15) The processor as in claim 15 wherein the specified masking operation comprises setting the bits of the data element in the destination register all equal to zero. ### Claim 18 (depends on 15) The processor as in claim 15 wherein the specified masking operation comprises maintaining existing values previously stored in the data element in the destination location. ### Claim 19 (depends on 15) The processor as in claim 15 wherein the destination location comprises a destination register. ### Claim 20 (depends on 15) The processor as in claim 15 wherein the destination location comprises a memory. ### Claim 21 (depends on 13) The processor as in claim 13 wherein the source operand value comprises a 128-bit value and the down-converted value comprises an 8-bit value. ### Claim 22 A computer system comprising: reading a source operand value to be down-converted from a first value to a down-converted value and stored in a destination location; reading each mask register bit stored in a mask register, the mask register bit(s) indicating whether to perform a masking operation or a conversion operation on the source operand value; if the mask register bit(s) indicates that a masking operation is to be performed, then performing a specified masking operation and storing the results of the masking operation in the destination location; and if the mask register bit(s) indicates that a masking operation is not to be performed, then down-converting the source operand value and storing the down-converted value in the specified destination location. ### Claim 23 (depends on 22) The system as in claim 22 wherein if the mask register bit(s) indicates that a masking operation is not to be performed, then determining whether to perform trunction or signed/unsigned saturation to generate the down-converted value and, based on the determination, performing trunction or signed/unsigned saturation to generate the down-converted value. ### Claim 24 (depends on 22) The system as in claim 22 wherein the specified masking operation comprises setting the bits of the data element in the destination register all equal to zero. ### Claim 25 (depends on 22) The system as in claim 22 wherein the specified masking operation comprises maintaining existing values previously stored in the data element in the destination location. ### Claim 26 (depends on 22) The system as in claim 22 wherein the destination location comprises a destination register. ### Claim 27 (depends on 20) The system as in claim 20 wherein the destination location comprises a memory. ### Claim 28 (depends on 22) The system as in claim 22 wherein the source operand value comprises a 128-bit value and the down-converted value comprises an 8-bit value.