# US 2014/0208074 A1 · Instruction scheduling for a multi-strand out-of-order processor

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- Number: US 2014/0208074 A1
- Document ID: US20140208074A1
- Status: Published application
- Kind: A1
- Application number: 13/993,552
- Filed: 2012-03-30
- Published: 2014-07-24
- Earliest claimed: 2012-03-30
- Inventors: Boris A. Babayan; Vladimir Pentkovski; Jayesh Iyer; Nikolay Kosarev; Sergey Y. Shishlov; Alexander V. Butuzov; Alexey Y. Sivtsov
- Web page: https://patentgrep.com/patent/US20140208074A1

## CPC

- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding}
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F 9/3854: {Instruction completion, e.g. retiring, committing or graduating}
- G06F 9/3858: {Result writeback, i.e. updating the architectural state or memory}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In one embodiment, a multi-strand system with a pipeline includes a front-end unit, an instruction scheduling unit (ISU), and a back-end unit. The front-end unit performs an out-of-order fetch of interdependent instructions queued using a front-end buffer. The ISU dedicates two hardware entries per strand for checking operand-readiness of an instruction and for determining an execution port to which the instruction is dispatched. The back-end unit receives instructions dispatched from the hardware device and stores the instructions until they are executed. Other embodiments are described and claimed.

## Claims

### Claim 1

A method, comprising:
fetching a strand of interdependent instructions for execution, wherein the strand of interdependent instructions are fetched out of order;
dedicating a first hardware resource and a second hardware resource for the strand;
storing an instruction of the strand using the first hardware resource;
determining whether the instruction stored using the first hardware resource is operand-ready;
storing the instruction using the second hardware resource when the instruction is operand-ready; and
determining an available execution port for the instruction stored using the second hardware resource.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
storing the fetched strand of interdependent instructions in a buffer with respect to execution order.

### Claim 3 (depends on 2)

The method of claim 2, wherein the buffer is in the front-end of an instruction scheduling unit for a multi-strand processor, and wherein the first hardware resource and the second hardware resource are inside of the instruction scheduling unit.

### Claim 4 (depends on 2)

The method of claim 2, wherein storing an instruction of the strand using the first hardware resource comprises:
selecting the instruction from a head of the buffer; and
storing the instruction using the first hardware resource when the first hardware resource is empty.

### Claim 5 (depends on 1)

The method of claim 1, wherein determining whether the instruction stored in the first hardware resource is operand-ready comprises:
performing an operand-ready check using one or more selected from the group consisting of scoreboard logic and tag comparison logic.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
determining, using a multiplexer and an instruction dispatch algorithm, the available execution port for the instruction stored in the second hardware resource.

### Claim 7

(canceled)

### Claim 8

An apparatus for scheduling instructions for execution, comprising:
a plurality of first level hardware entries to store instructions;
a plurality of second level hardware entries to store instructions; and
a hardware module to determine whether an instruction stored in any one of the first level hardware entries is operand-ready.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the apparatus is coupled to a front-end unit, the front-end unit to:
fetch a plurality of strands of interdependent instructions, wherein each strand is fetched out-of-order; and
store each one of the fetched strands in one of a plurality of buffers in the front-end unit.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the interdependent instructions stored in each one of the plurality of buffers are ordered in each one of the plurality of buffers with respect to execution order.

### Claim 11 (depends on 9)

The apparatus of claim 9, the apparatus to:
select an instruction from a head of one of the plurality of buffers; and
store the instruction using a first hardware level entry from the plurality of first level hardware entries.

### Claim 12 (depends on 9)

The apparatus of claim 9, wherein each one of the plurality of fetched strands corresponds with one of the plurality of first level hardware entries and one of the plurality of second level hardware entries.

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein a first level hardware entry dedicated to a first strand of interdependent instructions and a second level hardware entry dedicated to the first strand of interdependent instructions only store instructions associated with the first strand.

### Claim 14 (depends on 8)

The apparatus of claim 8, wherein the hardware module is to determine whether an instruction stored in any one of the first level hardware entries is operand-ready by using one or more selected from the group consisting of scoreboard logic and tag comparison logic.

### Claim 15 (depends on 8)

The apparatus of claim 8, further comprising:
a multiplexer to select instructions stored in any one of the second level hardware entries for dispatching to execution ports.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the multiplexer is further to dispatch an instruction stored in one of the second level hardware entries to an available execution port when the available execution port is determined for the instruction using an instruction dispatch algorithm.

### Claim 17 (depends on 8)

The apparatus of claim 8, wherein the hardware module is further to move an instruction stored using one of the plurality of first level hardware entries to one of the plurality of second level hardware entries when the instruction is determined operand-ready.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the one of the plurality of first level hardware entries and the one of the plurality of second level hardware entries are both dedicated to a common strand fetched by the front-end unit.

### Claim 19

(canceled)

### Claim 20

A system, comprising:
a dynamic random access memory (DRAM) coupled to a multi-core processor;
the multi-core processor, each core having at least one execution unit and an instruction scheduling unit, the instruction scheduling unit comprising:
a plurality of first level hardware entries to store instructions;
a plurality of second level hardware entries to store instructions; and
a hardware module to determine whether an instruction stored in any one of the plurality of first level hardware entries is operand-ready.

### Claim 21 (depends on 20)

The system of claim 20, wherein the instruction scheduling unit is coupled to a front-end unit comprising a plurality of buffers, the front-end unit to:
fetch a plurality of strands of interdependent instructions, wherein each strand is fetched out-of-order; and
store each one of the plurality of strands in one of the plurality of buffers with respect to execution order.

### Claim 22 (depends on 21)

The system of claim 21, the instruction scheduling unit to:
select an instruction from a head of one of the plurality of buffers; and
store the instruction using a first hardware level entry of the plurality of first level hardware entries.

### Claim 23

(canceled)

### Claim 24

(canceled)

### Claim 25

(canceled)

### Claim 26

(canceled)

### Claim 27

(canceled)

### Claim 28

(canceled)

### Claim 29

(canceled)

### Claim 30

(canceled)