# US 2014/0208073 A1 · Arithmetic Branch Fusion > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0208073 A1 - Document ID: US20140208073A1 - Status: Published application - Kind: A1 - Application number: 13/747,977 - Filed: 2013-01-23 - Published: 2014-07-24 - Earliest claimed: 2013-01-23 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Conrado Blasco-Allue; Sandeep Gupta - Web page: https://patentgrep.com/patent/US20140208073A1 ## CPC - G06F 9/30058: {Conditional branch instructions} - G06F 9/3001: {Arithmetic instructions} - G06F 9/30094: {Condition code generation, e.g. Carry, Zero flag} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/323: {for indirect branch instructions} - G06F 9/3804: {for branches, e.g. hedging, branch folding} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processor and method for fusing together an arithmetic instruction and a branch instruction. The processor includes an instruction fetch unit configured to fetch instructions. The processor may also include an instruction decode unit that may be configured to decode the fetched instructions into micro-operations for execution by an execution unit. The decode unit may be configured to detect an occurrence of an arithmetic instruction followed by a branch instruction in program order, wherein the branch instruction, upon execution, changes a program flow of control dependent upon a result of execution of the arithmetic instruction. In addition, the processor may further be configured to fuse together the arithmetic instruction and the branch instruction such that a single micro-operation is formed. The single micro-operation includes execution information based upon both the arithmetic instruction and the branch instruction. ## Claims ### Claim 1 A processor comprising: an instruction fetch unit configured to fetch instructions from a memory; and an instruction decode unit coupled to the instruction fetch unit and configured to decode fetched instructions into micro-operations for execution by an execution unit; wherein the decode unit is configured to detect an occurrence of an arithmetic instruction followed by a branch instruction in program order, wherein the branch instruction, upon execution, changes a program flow of control dependent upon a result of execution of the arithmetic instruction; and wherein the processor is further configured to fuse together the arithmetic instruction and the branch instruction such that a single micro-operation is formed, wherein the single micro-operation includes execution information based upon both the arithmetic instruction and the branch instruction. ### Claim 2 (depends on 1) The processor of claim 1, wherein the single micro-operation is executed in one execution cycle. ### Claim 3 (depends on 1) The processor of claim 1, wherein the conditional branch instruction comprises a compare branch which is conditional upon contents of a register specified in the instruction. ### Claim 4 (depends on 3) The processor of claim 3, wherein the arithmetic instruction includes at least a source register and a destination register. ### Claim 5 (depends on 4) The processor of claim 4, wherein the decode unit includes a fusion detect unit configured to detect that the destination register specified in the arithmetic instruction matches the register specified in the conditional branch instruction. ### Claim 6 (depends on 4) The processor of claim 4, wherein the arithmetic instruction when executed performs an arithmetic operation between at least two operands specified in the source and destination register and writes the result to the destination register, wherein the arithmetic operation includes a subtract operation (SUB), an addition operation (ADD), or reverse subtract operation (RSB). ### Claim 7 (depends on 1) The processor of claim 1, wherein the decode unit is further configured to: detect an occurrence of a logical instruction followed by the branch instruction in program order; and wherein the processor is further configured to fuse together the logical instruction and the branch instruction such that another single micro-operation is formed, wherein the another single micro-operation includes execution information based upon both the logical instruction and the branch instruction. ### Claim 8 (depends on 7) The processor of claim 7, wherein the logical instruction, when executed, performs a logical operation between at least two operands specified in the source and destination register and writes the result to the destination resister, wherein the logical operations include a logical OR (ORR) operation, a logical AND operation (AND), a logical Exclusive OR operation (EOR), or a bit clear operation (BIC). ### Claim 9 A method comprising: detecting an occurrence of a branch instruction subsequent to an arithmetic instruction, wherein the branch instruction, upon execution, changes a program flow of control dependent upon a result of execution of the arithmetic instruction; and fusing together the arithmetic instruction and the branch instruction such that a single micro-operation is formed, wherein the single micro-operation includes operations from both the arithmetic instruction and the branch instruction. ### Claim 10 (depends on 9) The method of claim 9, further comprising executing the single operation in one execution cycle. ### Claim 11 (depends on 10) The method of claim 10, wherein the conditional branch instruction comprises a compare branch zero (CBZ) which changes the program flow of control in response to detecting that contents of a register specified in the branch instruction are equal to zero. ### Claim 12 (depends on 10) The method of claim 10, wherein the conditional branch instruction comprises a compare branch not zero (CBNZ) which changes the program flow of control in response to detecting that contents of a register specified in the branch instruction are not equal to zero. ### Claim 13 (depends on 12) The method of claim 12, wherein detecting an occurrence of an arithmetic instruction followed by a branch instruction in program order includes detecting that a destination register specified in the arithmetic instruction matches the register specified in the conditional branch instruction. ### Claim 14 (depends on 12) The method of claim 12, further comprising: detecting an occurrence of a logical instruction followed by the branch instruction in program order; and fusing together the logical instruction and the branch instruction such that another single micro-operation is formed, wherein the another single micro-operation includes execution information based upon both the logical instruction and the branch instruction. ### Claim 15 A wireless mobile device comprising: a memory configured to store program instructions; and a processor coupled to the memory and configured to execute the program instructions, wherein the processor includes: an instruction fetch unit configured to fetch instructions from the memory; and an instruction decode unit coupled to the instruction fetch unit and configured to decode fetched instructions into micro-operations for execution by an execution unit; wherein the decode unit is configured to detect an occurrence of an arithmetic instruction followed by a branch instruction in program order, wherein the branch instruction, upon execution, changes a program flow of control dependent upon a result of execution of the arithmetic instruction; and wherein the processor is further configured to fuse together the arithmetic instruction and the branch instruction such that a single micro-operation is formed, wherein the single micro-operation includes execution information based upon both the arithmetic instruction and the branch instruction. ### Claim 16 (depends on 15) The wireless mobile device of claim 15, wherein the single micro-operation is executed in one execution cycle. ### Claim 17 (depends on 15) The wireless mobile device of claim 15, wherein the decode unit includes a fusion detect unit configured to detect that a destination register specified in the arithmetic instruction matches a register specified in the conditional branch instruction. ### Claim 18 (depends on 15) The wireless mobile device of claim 15, wherein the conditional branch instruction includes a compare branch zero (CBZ) which changes the program flow of control in response to detecting that contents of a register specified in the branch instruction are equal to zero, or a compare branch not zero (CBNZ) which changes the program flow of control in response to detecting that contents of a register specified in the branch instruction are not equal to zero. ### Claim 19 (depends on 15) The wireless mobile device of claim 15, wherein the decode unit is further configured to: detect an occurrence of a logical instruction followed by the branch instruction in program order; and wherein the processor is further configured to fuse together the logical instruction and the branch instruction such that another single micro-operation is formed, wherein the another single micro-operation includes execution information based upon both the logical instruction and the branch instruction. ### Claim 20 (depends on 19) The wireless mobile device of claim 19, wherein the logical instruction, when executed, performs a logical operation between at least two operands specified in the source and destination register and writes the result to the destination resister, wherein the logical operations include a logical OR (ORR) operation, a logical AND operation (AND), a logical Exclusive OR operation (EOR), or a bit clear operation (BIC).