# US 2014/0208070 A1 · Systems and methods for interfacing master and slave processors

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- Number: US 2014/0208070 A1
- Document ID: US20140208070A1
- Status: Published application
- Kind: A1
- Application number: 13/640,728
- Filed: 2011-12-14
- Published: 2014-07-24
- Earliest claimed: 2011-12-14
- Assignees: General Electric Company
- Applicants: General Electric Company
- Inventors: Daniel Milton Alley; Xiaomin Hu; Ye Xu
- Web page: https://patentgrep.com/patent/US20140208070A1

## CPC

- G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)}
- G06F 15/17: using an input/output type connection, e.g. channel, I/O port
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

System and methods are provided. In one embodiment, a system includes a first processor comprising a serial peripheral interface (SPI) port, and a second processor. The system further includes a galvanic isolation barrier. The system additionally includes a SPI bridge comprising a first output pin control configured to control a device. The SPI bridge additionally includes a first analog multiplexor control configured to route signals to a circuitry. The SPI bridge is configured to communicatively couple the first processor with the second processor through the galvanic isolation barrier, and to communicatively couple the first processor to the device through the first output pin control, and to route the signals between the first processor and the circuitry by using the first analog multiplexor control.

## Claims

### Claim 1

A system comprising:
a first processor comprising a serial peripheral interface (SPI) port;
a second processor;
a galvanic isolation barrier;
a SPI bridge comprising:
a first output pin control configured to control a device; and
a first analog multiplexor control configured to route signals to a circuitry, wherein the SPI bridge is configured to communicatively couple the first processor with the second processor through the galvanic isolation barrier, and to communicatively couple the first processor to the device through the first output pin control, and to route the signals between the first processor and the circuitry by using the first analog multiplexor control.

### Claim 2 (depends on 1)

The system of claim 1, wherein the galvanic isolation barrier comprises four pins configured to communicatively couple the galvanic isolation barrier to the SPI bridge.

### Claim 3 (depends on 2)

The system of claim 2, wherein the four pins comprise a master processor input (BSDI) pin, a master processor output (BSDO) pin, a master processor clock (BSCHK) pin, and a master processor select (BSEL) pin.

### Claim 4 (depends on 3)

The system of claim 3, wherein the SPI bridge comprises a mode sensing system configured to monitor the BSEL pin and to detect the transmission of a custom data pattern.

### Claim 5 (depends on 4)

The system of claim 4, wherein the custom data pattern comprises at least 4 1s, 4 0s, or a combination thereof.

### Claim 6 (depends on 3)

The system of claim 3, wherein the SPI bridge comprises a serial digital interface (SDI) combinatorial logic system configured to pulse the BSDI pin to transmit data incoming from the first processor through the isolation barrier and into the second processor.

### Claim 7 (depends on 1)

The system of claim 1, wherein the SPI bridge comprises a reply register configured to store a reply data based on a command from the second processor.

### Claim 8 (depends on 7)

The system of claim 7, wherein the reply data comprises a plurality of data transfers from the first processor.

### Claim 9 (depends on 1)

The system of claim 1, wherein the SPI bridge comprises a command register configured to interrupt the first register based on data incoming from the second processor.

### Claim 10 (depends on 1)

The system of claim 1, wherein the SPI bridge comprises a data multiplexor configured to communicatively couple the first processor to the first output pin control and to the first analog multiplexor control.

### Claim 11 (depends on 1)

The system of claim 1, wherein the first processor comprises a slave processor including only one of the SPI port, and the second processor comprises a master processor configured to issue commands to the slave processor.

### Claim 12

A method comprising:
transmitting data from a first processor through an isolation barrier;
determining if the data includes a custom pattern;
if the data does not includes the custom pattern, using a serial peripheral interface (SPI) communications protocol;
if the data includes the custom pattern, using a custom communications protocol;
transmitting the data to a second processor;
building a reply by using a reply register;
communicating the reply to the first processor through the isolation barrier.

### Claim 13 (depends on 12)

The method of claim 12, wherein the custom pattern comprises at least 4 1s, 4 0s, or a combination thereof.

### Claim 14 (depends on 12)

The method of claim 12, comprising transmitting the custom pattern at a baud rate faster than a baud rate used for asynchronous receiver/transmitter (UART) data transmissions.

### Claim 15 (depends on 12)

The method of claim 12, wherein transmitting the data to the second processor comprises using a single SPI port included in the second processor.

### Claim 16 (depends on 15)

The method of claim 15, comprising using the single SPI port to communicate with the first processor, with an output pin control, with an analog multiplexor control, or with a combination thereof.

### Claim 17

A system comprising:
a serial peripheral interface (SPI) bridge configured to communicatively couple a first processor having a SPI port to a second processor comprising:
a data multiplexor configured to route signals for the first processor;
a first register configured to communicatively couple the data multiplexor to the first processor;
an output pin control communicatively coupled to the data multiplexor and configured to control a device;
a serial digital interface (SDI) combinatorial logic system;
a second register communicatively coupled to a second processor through the SDI combinatorial logic system;
a reply register communicatively coupled to the data multiplexor, wherein the first processor is configured to use the data multiplexor to reply to a command issued by the second processor through an isolation barrier.

### Claim 18 (depends on 17)

The system of claim 17, comprising a mode sensing system configured to monitor the second processor for a custom data pattern and to enable the first processor to communicate by using a SPI protocol or a custom protocol based on the custom data pattern.

### Claim 19 (depends on 18)

The system of claim 18, wherein the mode sensing system is communicatively coupled to a processor select (BSEL) line of the isolation barrier to monitor the second processor for the custom data pattern.

### Claim 20 (depends on 17)

The system of claim 17, comprising an analog multiplexor control configured to route first processor signals incoming from the data multiplexor.