# US 2014/0208066 A1 · Vector generate mask instruction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0208066 A1 - Document ID: US20140208066A1 - Status: Published application - Kind: A1 - Application number: 13/748,538 - Filed: 2013-01-23 - Published: 2014-07-24 - Earliest claimed: 2013-01-23 - Assignees: International Business Machines Corporation - Inventors: Jonathan D. Bradbury; Robert F. Enenkel; Eric M. Schwarz; Timothy J. Slegel - Web page: https://patentgrep.com/patent/US20140208066A1 ## CPC - G06F 15/8053: {Vector processors} - G06F 9/3001: {Arithmetic instructions} - G06F 9/30018: {Bit or string instructions} - G06F 9/30021: {Compare instructions, e.g. Greater-Than, Equal-To, MINMAX} - G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE} - G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations} - G06F 9/30038: {using a mask} - G06F 9/30047: {Prefetch instructions; cache control instructions} - G06F 9/30098: {Register arrangements} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction. ## Claims ### Claim 1 A computer program product for executing a machine instruction in a central processing unit, the computer program product comprising: a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising: obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising: at least one opcode field to provide an opcode, the opcode identifying a Vector Generate Mask operation; a first register field to be used to designate a first register, the first register comprising a first operand; a first field to specify a starting position; and a second field to specify an ending position; and executing the machine instruction, the executing comprising: generating a mask for one or more elements of the first operand, the generating comprising setting one or more positions in the mask to a predefined value beginning at the starting position in the mask and ending at the ending position. ### Claim 2 (depends on 1) The computer program product of claim 1, wherein the one or more positions comprises one or more bits, and wherein the starting position specifies a first selected bit in the mask and the ending position specifies a second selected bit in the mask. ### Claim 3 (depends on 2) The computer program product of claim 2, wherein the first field comprises a first unsigned integer value specifying the starting position, and the second field comprises a second unsigned integer value specifying the ending position. ### Claim 4 (depends on 1) The computer program product of claim 1, wherein the generating comprises setting other positions in the mask to zero. ### Claim 5 (depends on 1) The computer program product of claim 1, wherein the executing further comprises: determining whether the starting position is greater than the ending position; and based on the starting position being greater than the ending position, a range of positions wraps at a maximum position for a size of the one or more elements of the first operand. ### Claim 6 (depends on 1) The computer program product of claim 1, wherein the machine instruction further comprises a field to specify the size of the one or more elements of the first operand. ### Claim 7 (depends on 1) The computer program product of claim 1, wherein the machine instruction further comprises an extension field to be used in designating one or more registers, and wherein the first register field is combined with a first portion of the extension field to designate the first register. ### Claim 8 A computer system for executing a machine instruction in a central processing unit, the computer system comprising: a memory; and a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising: obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising: at least one opcode field to provide an opcode, the opcode identifying a Vector Generate Mask operation; a first register field to be used to designate a first register, the first register comprising a first operand; a first field to specify a starting position; and a second field to specify an ending position; and executing the machine instruction, the executing comprising: generating a mask for one or more elements of the first operand, the generating comprising setting one or more positions in the mask to a predefined value beginning at the starting position in the mask and ending at the ending position. ### Claim 9 (depends on 8) The computer system of claim 8, wherein the one or more positions comprises one or more bits, and wherein the starting position specifies a first selected bit in the mask and the ending position specifies a second selected bit in the mask. ### Claim 10 (depends on 9) The computer system of claim 9, wherein the first field comprises a first unsigned integer value specifying the starting position, and the second field comprises a second unsigned integer value specifying the ending position. ### Claim 11 (depends on 8) The computer system of claim 8, wherein the generating comprises setting other positions in the mask to zero. ### Claim 12 (depends on 8) The computer system of claim 8, wherein the executing further comprises: determining whether the starting position is greater than the ending position; and based on the starting position being greater than the ending position, a range of positions wraps at a maximum position for a size of the one or more elements of the first operand. ### Claim 13 (depends on 8) The computer system of claim 8, wherein the machine instruction further comprises a field to specify the size of the one or more elements of the first operand. ### Claim 14 (depends on 8) The computer system of claim 8, wherein the machine instruction further comprises an extension field to be used in designating one or more registers, and wherein the first register field is combined with a first portion of the extension field to designate the first register. ### Claim 15 A method of executing a machine instruction in a central processing unit, the method comprising: obtaining, by a processor, a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction comprising: at least one opcode field to provide an opcode, the opcode identifying a Vector Generate Mask operation; a first register field to be used to designate a first register, the first register comprising a first operand; a first field to specify a starting position; and a second field to specify an ending position; and executing the machine instruction, the executing comprising: generating a mask for one or more elements of the first operand, the generating comprising setting one or more positions in the mask to a predefined value beginning at the starting position in the mask and ending at the ending position. ### Claim 16 (depends on 15) The method of claim 15, wherein the one or more positions comprises one or more bits, and wherein the starting position specifies a first selected bit in the mask and the ending position specifies a second selected bit in the mask. ### Claim 17 (depends on 16) The method of claim 16, wherein the first field comprises a first unsigned integer value specifying the starting position, and the second field comprises a second unsigned integer value specifying the ending position. ### Claim 18 (depends on 15) The method of claim 15, wherein the generating comprises setting other positions in the mask to zero. ### Claim 19 (depends on 15) The method of claim 15, wherein the executing further comprises: determining whether the starting position is greater than the ending position; and based on the starting position being greater than the ending position, a range of positions wraps at a maximum position for a size of the one or more elements of the first operand. ### Claim 20 (depends on 15) The method of claim 15, wherein the machine instruction further comprises a field to specify the size of the one or more elements of the first operand, and an extension field to be used in designating one or more registers, and wherein the first register field is combined with a first portion of the extension field to designate the first register.