# US 2014/0208060 A1 · Systems and methods for accessing memory

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- Number: US 2014/0208060 A1
- Document ID: US20140208060A1
- Status: Published application
- Kind: A1
- Application number: 13/746,141
- Filed: 2013-01-21
- Published: 2014-07-24
- Earliest claimed: 2013-01-21
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Robert Walker
- Web page: https://patentgrep.com/patent/US20140208060A1

## CPC

- G06F 12/1009: using page tables, e.g. page table structures
- G06F 9/5016: {the resource being the memory}
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 13/1684: {using multiple buses}
- G06F 2212/65: Details of virtual memory and virtual address translation
- G06F 2212/657: Virtual address space management
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory system including multiple physical channels is mapped into regions, such that any region spans each physical channel of the memory system. Applications are allocated memory in the regions, and performance and power requirements of the applications are associated with the regions. Additional methods and systems are also described.

## Claims

### Claim 1

A method of mapping a memory system having two or more physical channels, the method comprising:
mapping a region of the memory system to a requesting process, wherein each region of the memory system mapped to a respective requesting process includes at least a respective portion of each of the two or more physical channels.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
storing a value associated with the region, the value indicating a number of bytes to be accessed from each of the two or more physical channels before an address mapped to the region moves into a different physical channel.

### Claim 3 (depends on 2)

The method of claim 2, wherein the value is based on at least one of a performance requirement and a power requirement of the requesting process.

### Claim 4 (depends on 1)

The method of claim 1, wherein
each of the two or more physical channels comprises a respective plurality of rows of memory cells, and
the mapping includes mapping the region such that the region spans the two or more physical channels to include a same row of memory cells of each of the two or more physical channels.

### Claim 5 (depends on 4)

The method of claim 4, wherein
the region includes at least two same rows of memory cells of each of the two or more physical channels, and
one of the at least two rows of memory cells is not contiguous to one other of the at least two rows of memory cells.

### Claim 6

A method for accessing a memory system, the memory system including two or more physical channels, the method comprising:
receiving a request for access, the request including a logical memory address;
retrieving a channel depth associated with a region of the memory system that corresponds to the logical memory address, each region of the memory system distributed across the two or more physical channels to include at least a respective portion of each of the two or more physical channels, the respective portions being located at a same position within each of the two or more physical channels; and
performing an operation on the memory system in the region corresponding to the logical memory address, based on the retrieved channel depth and based on the request for access.

### Claim 7 (depends on 6)

The method of claim 6, wherein the logical memory address further comprises at least one bit for indicating the identity of the region to which the logical memory address has been mapped, and the at least one bit is added to the logical memory address by a processor making the access request.

### Claim 8 (depends on 6)

The method of claim 6, further comprising:
determining an address within the region on which to perform the requested operation using the received logical address, a starting physical address stored for the region and an ending physical address stored for the region.

### Claim 9 (depends on 6)

The method of claim 6, wherein retrieving a channel depth comprises retrieving a channel depth value of the region; and wherein performing an operation on the memory system based on the retrieved channel depth comprises determining, based on the channel depth value, a point at which to move a physical address within one of the physical channels to access the physical address.

### Claim 10 (depends on 9)

The method of claim 9, wherein performing an operation on the memory system further comprises accessing, in parallel, a respective memory cell from each of a number of the physical channels, the number being based on the channel depth value of the region.

### Claim 11

A method comprising:
receiving a memory allocation request; and
programming a data structure of a memory controller to include a start address and an end address for a region of a memory system based on the request, the memory system including a plurality of physical channels, each region of the memory system including at least a respective portion of each of the plurality of physical channels.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
receiving a second memory allocation request;
examining the data structure to determine a second start address for the second memory allocation; and
programming the data structure to include the second start address as the start address for a second region.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
receiving a request to access the region in the memory system, the request including an address for which access is requested;
appending at least one region-identifying bit to the address; and
communicating the address to a memory controller.

### Claim 14 (depends on 11)

The method of claim 11, wherein
the request includes a channel depth value indicating the number of bytes to be accessed from each of the plurality of physical channels of the memory system before an address mapped to the region moves into a different physical channel of the system, and
the region includes a number of rows of the plurality of physical channels based on the requirements of the application.

### Claim 15 (depends on 14)

The method of claim 14, wherein the channel depth value is based on at least one of a performance requirement and a power requirement of a process requesting the memory allocation.

### Claim 16

A memory controller for a memory system having at least two physical channels, the memory controller comprising:
a memory configured to store a data structure defining regions of the memory system, each region of the memory system comprising at least a respective portion of each of the two or more physical channels.

### Claim 17

A system comprising:
a memory system having two or more physical channels, each physical channel including a respective plurality of rows of memory cells;
a processor configured to map an application executing on the processor to a respective region of a plurality of regions of the memory system; and
a memory controller configured to store a data structure that defines the plurality of regions of the memory system, wherein each region of the plurality of regions of the memory system includes at least a respective portion of each of the two or more physical channels.

### Claim 18 (depends on 17)

The system of claim 17, wherein the memory is further configured to store a respective channel depth value for each of the regions, the channel depth value indicating a number of bytes to be accessed from each of the two or more physical channels before an address mapped to the region moves into a different physical channel.

### Claim 19

A computer-readable medium comprising instructions that, when implemented on a machine, cause the machine to:
request an allocation of memory in a memory system, the request including a performance point value that indicates a desired performance point for an application executing on the machine.

### Claim 20 (depends on 19)

The computer-readable medium of claim 19, wherein the performance point value is a desired channel depth at which memory transactions of the application will be performed.

### Claim 21 (depends on 19)

The computer-readable medium of claim 19, further comprising instructions to:
determine a desired performance point or power requirement for the application.

### Claim 22 (depends on 21)

The computer-readable medium of claim 21, wherein the desired performance point is determined based on the type of the application.

### Claim 23 (depends on 21)

The computer-readable medium of claim 21, wherein the desired performance point or power point is based on a value received from the application.

### Claim 24

A computer-readable medium comprising instructions that, when implemented on a machine, cause the machine to:
write a first address and a second address to a memory, the first address and the second address representing, respectively, a starting address of a region of a memory system to be allocated to a software application and an ending address of the region of the memory system, the memory system including two or more physical channels, and wherein each of the regions includes at least a respective portion of each of the two or more physical channels.

### Claim 25

A method of maintaining a memory map of a memory system having two or more physical channels, the method comprising:
storing a starting address and an ending address for a region of the memory map, the region including at least a respective portion of each of the two or more physical channels and the region comprising an amount of memory allocated to a first application;
storing a channel depth value based on at least one of a performance requirement and a power requirement of the first application, such that the channel depth value is associated with the region; and
updating the memory map with an additional starting address, an additional ending address, and an additional channel depth based on an allocation request for a second application.