# US 2014/0208047 A1 · Method and device to distribute code and data stores between volatile memory and non-volatile memory

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- Number: US 2014/0208047 A1
- Document ID: US20140208047A1
- Status: Published application
- Kind: A1
- Application number: 13/977,295
- Filed: 2011-12-28
- Published: 2014-07-24
- Earliest claimed: 2011-12-28
- Assignees: Intel Corporation
- Inventors: Balaji Vembu; Murali Ramadoss
- Web page: https://patentgrep.com/patent/US20140208047A1

## CPC

- G06F 3/0604: {Improving or facilitating administration, e.g. storage management}
- G06F 3/0631: {by allocating resources to storage systems}
- G06F 3/0638: {Organizing or formatting or addressing of data}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0683: {Plurality of storage devices}
- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 13/1668: {Details of memory controller}
- G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)}
- G06T 1/60: Memory management
- G11C 14/0045: {and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material}
- G11C 14/0081: {and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell}
- G11C 14/009: {and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material}
- G06F 2212/205: Hybrid memory, e.g. using both volatile and non-volatile memory
- G06F 2212/68: Details of translation look-aside buffer [TLB]
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A method, device, and system to distribute code and data stores between volatile and non-volatile memory are described. In one embodiment, the method includes storing one or more static code segments of a software application in a phase change memory with switch (PCMS) device, storing one or more static data segments of the software application in the PCMS device, and storing one or more volatile data segments of the software application in a volatile memory device. The method then allocates an address mapping table with at least a first address pointer to point to each of the one or more static code segments, at least a second address pointer to point to each of the one or more static data segments, and at least a third address pointer to point to each of the one or more volatile data segments.

## Claims

### Claim 1

A method comprising:
storing one or more static code segments of a software application in a phase change memory with switch (PCMS) device;
storing one or more static data segments of the software application in the PCMS device;
storing one or more volatile data segments of the software application in a volatile memory device;
allocating, an address mapping table with at least a first address pointer to point to each of the one or more static code segments, at least a second address pointer to point to each of the one or more static data segments, and at least a third address pointer to point to each of the one or more volatile data segments.

### Claim 2 (depends on 1)

The method of claim 1, wherein the storing of the static code segments, the static data segments, and the volatile data segments is performed during a loading of the software application for execution.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
reading a volatile bit variable for each of a set of data segments, wherein when the volatile bit is cleared, a given data segment of the set of data segments is stored as a static data segment, and wherein when the volatile bit is set, the given data segment of the set of data segments is stored as a volatile data segment.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
initially storing all data segments of the software application in the PCMS device;
for a given data segment within all of the data segments, transfer the given data segment to the volatile memory device when a rewrite request over the given data segment is received during execution of the software application.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
executing each static code segment and static data segment directly from the PCMS device without transferring to the volatile memory device.

### Claim 6 (depends on 1)

The method of claim 1, wherein the software application comprises firmware and the volatile memory device comprises a static random access memory (SRAM) device integrated into an embedded controller.

### Claim 7

A device comprising:
an embedded controller to
execute one or more static code segments of a firmware directly from a phase change memory with switch (PCMS) device;
execute one or more static data segments of the firmware directly from the PCMS device; and
execute one or more volatile data segments of the firmware from a static random access memory device integrated into the embedded controller.

### Claim 8 (depends on 7)

The device of claim 7, further comprising:
a cryptographic verification module to authenticate a new firmware code or data segment received from an external source;
wherein the embedded controller requires the authentication before the new firmware code or data segment is allowed to be executed.

### Claim 9

A system comprising:
a processor;
a volatile memory device to store memory allocation logic; and
a phase change memory with switch (PCMS) device;
wherein when the memory allocation logic is executed by the processor it causes the processor to
store one or more static code segments of a software application and one or more static data segments of the software application in the PCMS device;
store one or more volatile data segments of the software application in the volatile memory device; and
allocate an address mapping table in the volatile memory with at least a first address pointer to point to each of the one or more static code segments, at least as second address pointer to point to each of the one or more static data segments, and at least a third address pointer to point to each of the one or more volatile data segments.

### Claim 10 (depends on 9)

The system of claim 9, wherein the processor stores of the static code segments, the static data segments, and the volatile data segments during a loading of the software application for execution.

### Claim 11 (depends on 9)

The system of claim 9, wherein the processor reads a volatile bit variable for each of a set of data segments, wherein when the volatile bit is cleared, a given data segment of the set of data segments is stored as a static data segment, and wherein when the volatile bit is set, the given data segment of the set of data segments is stored as a volatile data segment.

### Claim 12 (depends on 9)

The system of claim 9, wherein the processor:
initially stores all data segments of the software application in the PCMS device;
for a given data segment within all of the data segments, transfers the given data segment to the volatile memory device when a rewrite request over the given data segment is received during execution of the software application.

### Claim 13 (depends on 9)

The system of claim 9, wherein the processor:
executes each static code segment and static data segment directly from the PCMS device without transferring to the volatile memory device.

### Claim 14 (depends on 9)

The system of claim 9, wherein the processor comprises an embedded controller, the software application comprises firmware, and the volatile memory device comprises a static random access memory (SRAM) device integrated into an embedded controller.