# US 2014/0208044 A1 · Semiconductor device and method of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0208044 A1 - Document ID: US20140208044A1 - Status: Published application - Kind: A1 - Application number: 13/844,914 - Filed: 2013-03-16 - Published: 2014-07-24 - Earliest claimed: 2013-01-22 - Assignees: SK hynix Inc. - Applicants: SK Hynix Inc. - Inventors: Eui Jin KIM - Web page: https://patentgrep.com/patent/US20140208044A1 ## CPC - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A method of operating a semiconductor device may comprise storing data in memory cells coupled to first word lines of memory blocks including the first word lines and second word lines located respectively between the first word lines, detecting a memory block, where data stored in the memory cells of the first word lines is invalidated, from the memory blocks, and storing data in memory cells coupled to the second word lines of the detected memory block. ## Claims ### Claim 1 A method of operating a semiconductor device, the method comprising: storing data in memory cells coupled to first word lines of memory blocks including the first word lines and second word lines located respectively between the first word lines; detecting a memory block, where data stored in the memory cells of the first word lines is invalidated, from the memory blocks; and storing data in memory cells coupled to the second word lines of the detected memory block. ### Claim 2 (depends on 1) The method of claim 1, wherein the detected memory block includes the second word lines coupled to memory cells of erase state. ### Claim 3 (depends on 1) The method of claim 1, wherein the memory block is detected after every data is stored in the memory cells of the first word lines included in the memory blocks. ### Claim 4 (depends on 1) The method of claim 1, wherein the data stored in the memory cells of the first word line or the second word line are invalidated in the event that the data stored in the memory cells of the first word line or the second word line are updated. ### Claim 5 (depends on 4) The method of claim 4, wherein the updated data is stored in memory cells of another word line in the event that the data stored in the memory cells of the first word line or the second word line are updated. ### Claim 6 (depends on 1) The method of claim 1, further comprising: performing an erase operation of the memory block where every data stored in the memory cells of the first word lines and the second word lines is invalidated. ### Claim 7 (depends on 1) The method of claim 1, further comprising: performing a garbage collection of a memory block including most number of memory cells where stored data is invalidated. ### Claim 8 (depends on 7) The method of claim 7, wherein the garbage collection is performed in the event that a memory block capable of storing data in the memory cells of the first word lines and a memory block capable of storing data in the memory cells of the second word lines are not detected. ### Claim 9 (depends on 1) The method of claim 1, wherein data is stored in memory cells of the other first word lines in the event that a memory block, where data is stored in only memory cells of a part of the first word lines, is detected, and data is stored in memory cells of the other second word lines in the event that a memory block, where data is stored in only memory cells of a part of the second word lines. ### Claim 10 (depends on 1) The method of claim 1, wherein the memory block is a log memory block in a memory array including data memory blocks and the log memory blocks. ### Claim 11 A semiconductor device comprising: memory blocks, each memory block including first word lines and second word lines located respectively between the first word lines; and a peripheral circuit configured to store data in memory cells coupled to the first word lines of the memory blocks, and store data in memory cells coupled to the second word lines of detected memory block in the event that a memory block, where every data stored in the memory cells of the first word lines is invalidated, is detected from the memory blocks. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein the memory blocks include data memory blocks and log memory blocks, and the peripheral circuit detects the memory block after every data is stored in the memory cells of the first word lines included in the log memory blocks. ### Claim 13 (depends on 11) The semiconductor device of claim 11, wherein the peripheral circuit invalidates the data stored in the memory cells of the first word line or the second word line in the event that the data stored in the memory cells of the first word line or the second word line are updated. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the peripheral circuit stores the updated data in memory cells of another word line, when the data stored in the memory cells of the first word line or the second word line are updated. ### Claim 15 (depends on 11) The semiconductor device of claim 11, wherein the peripheral circuit performs an erase operation of a memory block where every data stored in the memory cells of the first word lines and the second word lines is invalidated. ### Claim 16 (depends on 11) The semiconductor device of claim 11, wherein the peripheral circuit performs a garbage collection of a memory block including most number of memory cells where the stored data is invalidated. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein the peripheral circuit performs the garbage collection in the event that a memory block capable of storing data in memory cells of the first word lines or the second word lines is not detected. ### Claim 18 (depends on 18) The semiconductor device of claim 18, wherein the peripheral circuit stores data in memory cells of the other first word lines in the event that a memory block, where data is stored in only memory cells of a part of the first word lines, is detected, and stores data in memory cells of the other second word lines in the event that a memory block, where data is stored in only memory cells of a part of the second word lines, is detected. ### Claim 19 A semiconductor device comprising: a memory device configured to include memory blocks, each memory block including first word lines and second word lines located respectively between the first word lines; and a memory controller configured to control the memory device to store data in first memory cells coupled to the first word lines of a memory block selected from the memory blocks, and change a physical address to a logical address and output the logical address to the memory device, to store data in second memory cells coupled to the second word lines in the event that the data stored in the first memory cells are invalidated. ### Claim 20 (depends on 19) The semiconductor device of claim 19, wherein the memory device performs a garbage collection of a memory block including most number of memory cells where the stored data is invalidated.