# US 2014/0208041 A1 · Memory circuitry including computational circuitry for performing supplemental functions

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- Number: US 2014/0208041 A1
- Document ID: US20140208041A1
- Status: Published application
- Kind: A1
- Application number: 13/841,042
- Filed: 2013-03-15
- Published: 2014-07-24
- Earliest claimed: 2012-11-15
- Assignees: Elwha LLC
- Inventors: Roderick A. Hyde; Nicholas F. Pasch; Clarence T. Tegreene
- Web page: https://patentgrep.com/patent/US20140208041A1

## CPC

- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 13/16: for access to memory bus (G06F13/28 takes precedence)
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A computer system includes but is not limited to a primary processing circuitry, a bus coupled to the primary processing circuitry, and memory circuitry coupled to the bus. The memory circuitry is physically separated from the primary processing circuitry. The memory circuitry includes at least one integrated memory circuit and computational circuitry. The at least one integrated memory circuit configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry. The computational circuitry co-located with the at least one integrated memory circuit, the computational circuitry co-located with integrated memory circuit can be configured for performing supplemental functions at least partially during time periods that are not accessing intervals.

## Claims

### Claim 1

A computer system comprising:
primary processing circuitry;
a bus coupled to the primary processing circuitry; and
memory circuitry coupled to the bus, the memory circuitry physically separated from the primary processing circuitry, the memory circuitry including:
at least one integrated memory circuit configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry; and
computational circuitry co-located with the at least one integrated memory circuit, the computational circuitry co-located with integrated memory circuit being configured for performing supplemental functions at least partially during time periods that are not accessing intervals.

### Claim 2 (depends on 1)

The computer system according to claim 1 wherein:
the computational circuitry co-located with integrated memory circuit is configured to present supplementally calculated data in coordination with the requested data.

### Claim 3 (depends on 1)

The computer system according to claim 1 wherein the supplemental functions include at least:
searching.

### Claim 4 (depends on 1)

The computer system according to claim 1 wherein the supplemental functions include at least:
sorting.

### Claim 5 (depends on 1)

The computer system according to claim 1 wherein the supplemental functions include at least:
accessing and creating indices for databases.

### Claim 6 (depends on 1)

The computer system according to claim 1 wherein the supplemental functions include at least:
array computations.

### Claim 7 (depends on 6)

The computer system according to claim 6 wherein the array computations include at least:
least squares computations;
maximum, minimum, and/or equality computations; and
statistical computation.

### Claim 8 (depends on 1)

The computer system according to claim 1 wherein the supplemental functions include at least:
garbage collection.

### Claim 9

A system comprising:
memory storage circuitry configured for interaction with a memory bus; and
memory control circuitry co-integrated and co-located with memory storage circuitry, the memory control circuitry being configured for Restricted Cache Coherence Protocol.

### Claim 10 (depends on 9)

The system according to claim 9 wherein:
the Restricted Cache Coherence Protocol is a function of at least one processor coupled to the memory bus.

### Claim 11 (depends on 9)

The system according to claim 9 wherein:
the Restricted Cache Coherence Protocol restricts the memory control circuitry to read/write with the co-integrated and co-located memory storage circuitry.

### Claim 12

A method of local computation in a memory device comprising:
locally determining whether a memory line has been checked out for writing;
upon determining that the memory line has not been checked out for writing, retrieving data from at least one location associated with the memory line; and
performing a local action and/or computation involving the retrieved data.

### Claim 13 (depends on 12)

The method of local computation in the memory device according to claim 12 further comprising:
upon determining that the memory line has been checked out for writing, receiving an indication that the memory line has become available;
after receiving an indication that the memory line has become available, retrieving data from at least one location associated with the memory line; and
performing a local action and/or computation involving the retrieved data.

### Claim 14 (depends on 12)

The method of local computation in the memory device according to claim 12 further comprising:
upon determining that the memory line has been checked out for writing, requesting access to the checked out memory line;
after requesting access to the checked out memory line, retrieving data from at least one location associated with the memory line; and
performing a local action and/or computation involving the retrieved data.

### Claim 15

A method of providing data to a memory bus comprising:
retrieving in a first memory device a first data set;
performing at the first memory device a first local action and/or computation involving the retrieved first data set;
providing an indication directly to a second memory device coupled to the memory bus of a status of the first local action and/or computation; and
performing a second local action and/or computation at the second memory device responsive to the provided indication.

### Claim 16 (depends on 15)

The method of providing data to the memory bus according to claim 15 further comprising:
directing a message to the second memory device of a status of the first local computation; and
performing at the second memory device a second local action and/or computation responsive to the directed message.

### Claim 17

A method of performing a computation comprising:
performing a local action and/or computation at a first memory device; and
defining a retrieval strategy for the first memory device based on the local action and/or computation at a first memory device.

### Claim 18 (depends on 17)

The method of performing a computation according to claim 17 wherein:
the defined retrieval strategy is a prefetch strategy.

### Claim 19 (depends on 17)

The method of performing a computation according to claim 17 further comprising:
retrieving data from the first memory device using the defined retrieval strategy.

### Claim 20 (depends on 17)

The method of performing a computation according to claim 17 wherein defining a retrieval strategy for the first memory device based on the local action and/or computation at the first memory device includes:
defining the retrieval strategy according to a Markov model.

### Claim 21 (depends on 17)

The method of performing a computation according to claim 17 further comprising:
retrieving Markov data from a Markov location in the first memory device.

### Claim 22 (depends on 17)

The method of performing a computation according to claim 17 wherein performing a local action and/or computation at the first memory device includes:
determining a stride length.

### Claim 23 (depends on 17)

The method of performing a computation according to claim 17 wherein performing a local action and/or computation at the first memory device includes:
determining a stream sequence.

### Claim at position 24

-35. (canceled)