# US 2014/0208031 A1 · Apparatus and method for memory-hierarchy aware producer-consumer instructions

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- Number: US 2014/0208031 A1
- Document ID: US20140208031A1
- Status: Published application
- Kind: A1
- Application number: 13/994,724
- Filed: 2011-12-21
- Published: 2014-07-24
- Earliest claimed: 2011-12-21
- Inventors: Shlomo Raikin; Robert Valentine; Raanan Sade; Julius Yuli Mandelbalt; Ron Shalev; Larisa Novakovsky
- Web page: https://patentgrep.com/patent/US20140208031A1

## CPC

- G06F 12/0811: with multilevel cache hierarchies
- G06F 9/3828: {with global bypass, e.g. between pipelines, between clusters}
- G06F 9/3891: {organised in groups of units sharing resources, e.g. clusters}
- G06F 12/0891: using clearing, invalidating or resetting means
- G06T 1/60: Memory management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL

## Abstract

An apparatus and method are described for efficiently transferring data from a producer core to a consumer core within a central processing unit (CPU). For example, one embodiment of a method comprises: A method for transferring a chunk of data from a producer core of a central processing unit (CPU) to consumer core of the CPU, comprising: writing data to a buffer within the producer core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core; and upon the consumer core detecting that data is available in the cache, providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core.

## Claims

### Claim 1

A method for transferring a chunk of data from a producer core of a central processing unit (CPU) to consumer core of the CPU, comprising:
writing data to a buffer within the producer core of the CPU until a designated amount of data has been written;
upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core;
setting an indication to indicate to the consumer core that data is available in the cache; and
upon the consumer core detecting the indication, providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core.

### Claim 2 (depends on 1)

The method as in claim 1 wherein the indication comprises a flag writable by the core and readable by the consumer core.

### Claim 3 (depends on 2)

The method as in claim 2 wherein the flag comprises a binary value indicative having a first value indicating that the data is available in the cache and a second value indicating that data is not available in the cache.

### Claim 4 (depends on 1)

The method as in claim 1 wherein the consumer core reads the indication via a polling technique in which the consumer core periodically reads polls for the indication.

### Claim 5 (depends on 1)

The method as in claim 1 wherein the consumer core reads the indication in response to an interrupt signal.

### Claim 6 (depends on 1)

The method as in claim 1 wherein the operations of the method are executed by the producer core in response to the execution of a first instruction by the producer core.

### Claim 7 (depends on 6)

The method as in claim 6 wherein the first instruction comprises a MovNonAllocate store instruction.

### Claim 8 (depends on 6)

The method as in claim 6 further comprising:
permitting the first instruction to be interleaved with a plurality of other instructions of the same instruction type.

### Claim 9 (depends on 8)

The method as in claim 8 further comprising:
permitting the first instruction to be interleaved with a plurality of other instructions of different instruction types.

### Claim 10 (depends on 9)

The method as in claim 9 wherein the other instructions are write-back store instructions and the first instruction is a MovNonAllocate store instruction.

### Claim 11 (depends on 1)

The method as in claim 1 wherein the buffer within the producer core is a fill buffer and wherein the cache accessible by both the producer core and the consumer core is a level 3 (L3) cache.

### Claim 12

An instruction processing apparatus comprising:
a producer core within a central processor unit (CPU) producing data for one or more consumer cores and a cache accessible by the producer core and the one or more consumer cores;
core-core producer-consumer logic configured to perform the operations of:
writing data to a buffer within the producer core of the CPU until a designated amount of data has been written;
upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core;
setting an indication to indicate to the consumer core that data is available in the cache; and
upon the consumer core detecting the indication, providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core.

### Claim 13 (depends on 12)

The instruction processing apparatus as in claim 12 wherein the indication comprises a flag writable by the core and readable by the consumer core.

### Claim 14 (depends on 13)

The instruction processing apparatus as in claim 13 wherein the flag comprises a binary value indicative having a first value indicating that the data is available in the cache and a second value indicating that data is not available in the cache.

### Claim 15 (depends on 12)

The instruction processing apparatus as in claim 12 wherein the consumer core reads the indication via a polling technique in which the consumer core periodically reads polls for the indication.

### Claim 16 (depends on 12)

The instruction processing apparatus as in claim 12 wherein the consumer core reads the indication in response to an interrupt signal.

### Claim 17 (depends on 12)

The instruction processing apparatus as in claim 12 wherein the operations of the instruction processing apparatus are executed by the producer core in response to the execution of a first instruction by the producer core.

### Claim 18 (depends on 17)

The instruction processing apparatus as in claim 17 wherein the first instruction comprises a MovNonAllocate store instruction.

### Claim 19 (depends on 17)

The instruction processing apparatus as in claim 17 wherein the core-core producer-consumer logic performs the additional operations of:
permitting the first instruction to be interleaved with a plurality of other instructions of the same instruction type.

### Claim 20 (depends on 19)

The instruction processing apparatus as in claim 19 wherein the core-core producer-consumer logic performs the additional operations of:
permitting the first instruction to be interleaved with a plurality of other instructions of different instruction types.

### Claim 21 (depends on 20)

The instruction processing apparatus as in claim 20 wherein the other instructions are write-back store instructions and the first instruction is a MovNonAllocate store instruction.

### Claim 22 (depends on 12)

The instruction processing apparatus as in claim 12 wherein the buffer within the producer core is a fill buffer and wherein the cache accessible by both the producer core and the consumer core is a level 3 (L3) cache.

### Claim 23

A computer system comprising:
a graphics processor unit (GPU) for processing a set of graphics instructions to render video; and
a central processing unit comprising:
a producer core within a central processor unit (CPU) producing data for one or more consumer cores and a cache accessible by the producer core and the one or more consumer cores;
core-core producer-consumer logic configured to perform the operations of:
writing data to a buffer within the producer core of the CPU until a designated amount of data has been written;
upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core;
setting an indication to indicate to the consumer core that data is available in the cache; and
upon the consumer core detecting the indication, providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core.

### Claim 24

An apparatus for transferring a chunk of data from a producer core of a central processing unit (CPU) to consumer core of the CPU, comprising:
means for writing data to a buffer within the producer core of the CPU until a designated amount of data has been written;
means for responsively generating an eviction cycle upon detecting that the designated amount of data has been written, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core;
means for setting an indication to indicate to the consumer core that data is available in the cache; and
means for providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core.

### Claim 25 (depends on 24)

The apparatus as in claim 24 wherein the indication comprises a flag writable by the core and readable by the consumer core.

### Claim 26 (depends on 25)

The apparatus as in claim 25 wherein the flag comprises a binary value indicative having a first value indicating that the data is available in the cache and a second value indicating that data is not available in the cache.

### Claim 27 (depends on 24)

The apparatus as in claim 24 wherein the consumer core reads the indication via a polling technique in which the consumer core periodically reads polls for the indication.

### Claim 28 (depends on 24)

The apparatus as in claim 24 wherein the consumer core reads the indication in response to an interrupt signal.

### Claim 29 (depends on 24)

The apparatus as in claim 24 wherein the operations by the producer core are executed in response to the execution of a first instruction by the producer core.

### Claim 30 (depends on 29)

The apparatus as in claim 29 wherein the first instruction comprises a MovNonAllocate store instruction.

### Claim 31

(canceled)

### Claim 32

(canceled)

### Claim 33

(canceled)

### Claim 34

(canceled)