# US 2014/0208029 A1 · Use of flash cache to improve tiered migration performance

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- Number: US 2014/0208029 A1
- Document ID: US20140208029A1
- Status: Published application
- Kind: A1
- Application number: 13/746,973
- Filed: 2013-01-22
- Published: 2014-07-24
- Earliest claimed: 2013-01-22
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Michael T. BENHASE; Lokesh M. GUPTA
- Web page: https://patentgrep.com/patent/US20140208029A1

## CPC

- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0608: {Saving storage space on storage systems}
- G06F 3/0613: {in relation to throughput}
- G06F 3/0647: {Migration mechanisms}
- G06F 3/065: {Replication mechanisms}
- G06F 3/0673: {Single storage device}
- G06F 3/0683: {Plurality of storage devices}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0842: for multiprocessing or multitasking
- G06F 12/0866: for peripheral storage systems, e.g. disk cache
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 2212/608: Details relating to cache mapping
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, and at a time in which at least one data segment is to be migrated from one level to another level of the tiered levels of storage, a data migration mechanism is initiated by copying data resident in the lower-speed cache corresponding to the at least one data segment to be migrated to a target on the another level, and reading remaining data, not previously copied from the lower-speed cache, from a source on the one level, and writing the remaining data to the target.

## Claims

### Claim at position 1

1-7. (canceled)

### Claim 8

A system for data processing in a computing storage environment, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, comprising:
a processor device, operable in the computing storage environment, wherein the processor device:
at a time in which at least one data segment is to be migrated from one level to another level of the tiered levels of storage, initiates a data migration mechanism by:
copying data resident in the lower-speed cache corresponding to the at least one data segment to be migrated to a target on the another level, and
reading remaining data, not previously copied from the lower-speed cache, from a source on the one level, and writing the remaining data to the target.

### Claim 9 (depends on 8)

The system of claim 8, wherein the processor device, during the reading and the writing of the remaining data, allows destages of updates corresponding to the at least one data segment to proceed to the lower-speed cache in lieu of abstaining from destaging the updates to the source.

### Claim 10 (depends on 9)

The system of claim 9, wherein the processor device changes a logical address of the at least one data segment to point to the target.

### Claim 11 (depends on 9)

The system of claim 9, wherein the processor device, subsequent to the reading and the writing of the remaining data, destages the updates from either the higher and lower speed caches to the target.

### Claim 12 (depends on 8)

The system of claim 8, wherein the processor device, pursuant to copying the data resident in the lower-speed cache, identifies the resident data as having been copied.

### Claim 13 (depends on 8)

The system of claim 8, wherein the processor device, if at least one of the lower-speed cache is inaccessible and the lower-speed cache is filled with additional modified data to be subsequently destaged:
initiates an alternate data migration mechanism whereby all data is read from the source and destaged to the target, while all destages of updates corresponding to the at least one data segment are withheld until the all data is destaged to the target.

### Claim 14 (depends on 8)

The system of claim 8, wherein the processor device performs initiating the data movement mechanism based on an observation of a heat metric.

### Claim 15

A computer program product for data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising:
a first executable portion that:
at a time in which at least one data segment is to be migrated from one level to another level of the tiered levels of storage, initiates a data migration mechanism by:
copying data resident in the lower-speed cache corresponding to the at least one data segment to be migrated to a target on the another level, and
reading remaining data, not previously copied from the lower-speed cache, from a source on the one level, and writing the remaining data to the target.

### Claim 16 (depends on 15)

The computer program product of claim 15, further including a second executable portion that, during the reading and the writing of the remaining data, allows destages of updates corresponding to the at least one data segment to proceed to the lower-speed cache in lieu of abstaining from destaging the updates to the source.

### Claim 17 (depends on 16)

The computer program product of claim 16, further including a third executable portion that changes a logical address of the at least one data segment to point to the target.

### Claim 18 (depends on 16)

The computer program product of claim 16, further including a third executable portion that, subsequent to the reading and the writing of the remaining data, destages the updates from either the higher and lower speed caches to the target.

### Claim 19 (depends on 15)

The computer program product of claim 15, further including a second executable portion that, pursuant to copying the data resident in the lower-speed cache, identifies the resident data as having been copied.

### Claim 20 (depends on 15)

The computer program product of claim 15, further including a second executable portion that, if at least one of the lower-speed cache is inaccessible and the lower-speed cache is filled with additional modified data to be subsequently destaged:
initiates an alternate data migration mechanism whereby all data is read from the source and destaged to the target, while all destages of updates corresponding to the at least one data segment are withheld until the all data is destaged to the target.

### Claim 21 (depends on 15)

The computer program product of claim 15, further including a second executable portion that performs initiating the data movement mechanism based on an observation of a heat metric.