# US 2014/0208015 A1 · Memory control system and power control method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0208015 A1 - Document ID: US20140208015A1 - Status: Published application - Kind: A1 - Application number: 14/222,767 - Filed: 2014-03-24 - Published: 2014-07-24 - Earliest claimed: 2011-09-28 - Assignees: Panasonic Corporation - Applicants: Panasonic Corporation - Inventors: Takashi MUROYAMA; Akira TAKAHASHI - Web page: https://patentgrep.com/patent/US20140208015A1 ## CPC - G06F 3/0653: {Monitoring storage devices or systems} - G06F 1/3225: of memory devices - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G06F 3/061: {Improving I/O performance} - G06F 3/0673: {Single storage device} - G06F 12/023: {Free address space management} - G06F 12/06: Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) - G06F 2212/1028: Power efficiency - G06F 2212/2532: comprising a plurality of modules - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A memory control system includes: a plurality of I/O circuits; and a power control circuit that performs, when a predetermined condition for usage states of memories is satisfied, and an unused memory is present among the memories, a power consumption reduction process for causing a target I/O circuit to consume less power than an other one of the I/O circuits, the target I/O circuit being an I/O circuit among the I/O circuits that is connected to the unused memory. ## Claims ### Claim 1 A memory control system connected to a plurality of memories, the memory control system comprising: a plurality of I/O circuits; and a monitoring circuit that monitors usage states of the memories, wherein each of the I/O circuits is connected t one of the memories, when one of the memories is accessed, each of the I/O circuits that is connected thereto is used, the I/O circuit consumes power to operate, and the monitoring circuit determines, among the memories, a memory to which access is permitted, based on the usage states of the memories, the memory control system further comprising a power control circuit that performs, when a predetermined condition for the usage states of the memories is satisfied, and an unused memory is present among the memories, a power consumption reduction process for causing a target I/O circuit to consume less power than an other one of the I/O circuits, the target I/O circuit being an I/O circuit among the I/O circuits that is connected to the unused memory, wherein the memories are set to have an n number of segments, n being an integer greater than or equal to 2, each of the n number of the segments corresponds to all or part of a plurality of regions identified by the same address for the memories, and the memories are accessed on a segment basis, the memory control system further comprising a memory management circuit that (a) makes, every time an instruction to perform an access process for accessing one of the n number of the segments is received, the segment to be accessed valid and (b) makes, every time a predetermined process for causing the access process at least once is completed, the segment to be accessed invalid, wherein the monitoring circuit determines, among the memories, the memory to which access is permitted, based on the number of valid segments among the n number of the segments. ### Claim 2 (depends on 1) The memory control system according to claim 1, wherein each of the I/O circuits includes a circuit used when the one of the memories connected to the I/O circuit is accessed, and the power control circuit performs the power consumption reduction process for causing the target. I/O circuit to disable the circuit included in the I/O circuit that is the target I/O circuit. ### Claim 3 (depends on 1) The memory control system according to claim 1, wherein the predetermined condition is a condition that a value dependent on the number of latest valid segments is less than or equal to a predetermined first threshold value. ### Claim 4 (depends on 3) The memory control system according to claim 3, wherein the value dependent on the number of the latest valid segments is a ratio of the number of the latest valid segments to n. ### Claim 5 (depends on 4) The memory control system according to claim 4, wherein the first threshold value is less than 0.5. ### Claim 6 (depends on 1) The memory control system according to claim 1, wherein each of the memories is assigned a different priority level, each of the n number of the segments is associated with segment information including memory usage information for identifying, among the memories, the memory to which access is permitted, and the monitoring circuit determines, among the memories, the memory to which access is permitted, by updating, every time a process for accessing one of the n number of the segments is performed, the memory usage information included in the segment information so that access to, among the memories, a memory having a higher priority level as a memory corresponding to the segment to be accessed is permitted as the number of the valid segments is less. ### Claim 7 (depends on 1) The memory control system according to claim 1, further comprising a plurality of functional circuits, wherein each of the functional circuits performs a different process, and the monitoring circuit determines, among the memories, the memory to which access is permitted, based on a maximum memory capacity used in the process performed by each functional circuit. ### Claim 8 (depends on 1) The memory control system according to claim 1, wherein each of the I/O circuits is a circuit that uses a differential signal. ### Claim 9 A power control method performed by a memory control system connected to a plurality of memories, wherein the memory control system includes: a plurality of I/O circuits; and a monitoring circuit that monitors usage states of the memories, each of the I/O circuits is connected to one of the memories, when one of the memories is accessed, each of the I/O circuits that is connected thereto is used, the I/O circuit consumes power to operate, and the monitoring circuit determines, among the memories, a memory to which access is permitted, based on the usage states of the memories, the power control method comprising performing, when a predetermined condition for the usage states of the memories is satisfied, and an unused memory is present among the memories, a power consumption reduction process for causing a target I/O circuit to consume less power than an other one of the I/O circuits, the target I/O circuit being an I/O circuit among the I/O circuits that is connected to the unused memory, wherein the memories are set to have an n number of segments, n being an integer greater than or equal to 2, each of the n number of the segments corresponds to all or part of a plurality of regions identified by the same address for the memories, and the memories are accessed on a segment basis, the power control method further comprising (a) making, every time an instruction to perform an access process for accessing one of the n number of the segments is received, the segment to be accessed valid and (b) making, every time a predetermined process for causing the access process at least once is completed, the segment to be accessed invalid, and wherein the monitoring circuit determines, among the memories, the memory to which access is permitted, based on the number of valid segments among the n number of the segments.