# US 2014/0208003 A1 · Variable-size flash translation layer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0208003 A1 - Document ID: US20140208003A1 - Status: Published application - Kind: A1 - Application number: 14/055,336 - Filed: 2013-10-16 - Published: 2014-07-24 - Earliest claimed: 2013-01-22 - Assignees: LSI Corporation - Applicants: LSI Corporation - Inventors: Earl T. Cohen - Web page: https://patentgrep.com/patent/US20140208003A1 ## CPC - G06F 12/1009: using page tables, e.g. page table structures - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/064: {Management of blocks} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0661: {Format or protocol conversion arrangements} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G06F 12/02: Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)} - G06F 12/10: Address translation - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 29/04: Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G06F 12/04: Addressing variable-length words or parts of words - G06F 2212/2022: Flash memory - G06F 2212/401: Compressed data - G06F 2212/7201: Logical to physical mapping or translation of blocks or pages - G06F 2212/7202: Allocation control and policies - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A method for using a variable-size flash transition layer is disclosed. Step (A) receives a read request to read data corresponding to a logical block address from a nonvolatile memory. Step (B) reads a particular entry of a map to obtain (i) a physical address of a particular page of the nonvolatile memory, (ii) an offset in the particular page to compressed data previously stored and (iii) a length of the compressed data. The particular entry is associated with the logical block address. Step (C) converts the offset and the length to (i) an address of a given read unit in the particular page and (ii) a number of the read units to be read. Step (D) reads from the particular page at most the number of the read units starting from the given read unit. An offset and length granularity are finer than one read unit. ## Claims ### Claim 1 A method for using a variable-size flash transition layer, comprising the steps of: (A) receiving, at an apparatus from a host, a read request to read particular data corresponding to a logical block address from a nonvolatile memory of said apparatus; (B) reading a particular one of a plurality of entries in a map to obtain (i) a physical address of a particular one of a plurality of pages of said nonvolatile memory, (ii) an offset in said particular page to compressed data previously stored in response to writing said compressed data corresponding to said logical block address and (iii) a length of said compressed data, wherein said particular entry is associated with said logical block address; (C) converting said offset and said length to (i) an address of a given one of a plurality of read units in said particular page and (ii) a number of said read units to be read from said particular page; and (D) reading from said particular page at most said number of said read units starting from said given read unit, wherein a granularity of said offset and said length is finer than a size of one of said read units. ### Claim 2 (depends on 1) The method according to claim 1, further comprising the steps of: performing error correction decoding on each of said read units as read from said particular page to generate corrected data; and extracting said compressed data from said corrected data according to both (i) said offset in said particular page to said compressed data and (ii) said length of said compressed data. ### Claim 3 (depends on 2) The method according to claim 2, further comprising the steps of: decompressing said compressed data to generate return data; and transferring said return data to said host. ### Claim 4 (depends on 1) The method according to claim 1, wherein said number of said read units to be read is less than all of said read units in said particular page. ### Claim 5 (depends on 1) The method according to claim 1, further comprising the step of: determining that at least a portion of said compressed data is in one or more subsequent read units of a subsequent one of said pages of said nonvolatile memory based on both (i) said offset in said particular page to said compressed data and (ii) said length of said compressed data combined with an amount of user data in said particular page. ### Claim 6 (depends on 5) The method according to claim 5, further comprising the step of: reading from said subsequent page at most said one or more subsequent read units. ### Claim 7 (depends on 1) The method according to claim 1, wherein (i) a first one of said pages of said nonvolatile memory includes a first number of said read units, (ii) a second one of said pages of said nonvolatile memory includes a second number of said read units and (iii) said first number is different from said second number. ### Claim 8 (depends on 1) The method according to claim 1, wherein (i) a first one of said pages of said nonvolatile memory includes a first amount of user data, (ii) a second one of said pages of said nonvolatile memory includes a second amount of said user data and (iii) said first amount is different from said second amount. ### Claim 9 (depends on 1) The method according to claim 1, further comprising the steps of: receiving a write request to write said particular data in said nonvolatile memory; compressing said particular data to generate said compressed data that is smaller than said particular data; writing in said particular page at least a portion of said compressed data; and storing in said particular entry (i) said physical address of said particular page, (ii) said offset in said particular page to said compressed data and (iii) said length of said compressed data. ### Claim 10 (depends on 9) The method according to claim 9, further comprising the step of: writing in said particular page a header that includes at least a portion of said logical block address of said write request and said length. ### Claim 11 (depends on 1) The method according to claim 1, wherein (i) said logical block address is one of a plurality of logical block addresses and (ii) at least one of said read units of said number of said read units includes at least some different data corresponding to a different one of said logical block addresses. ### Claim 12 (depends on 1) The method according to claim 1, wherein at least one of said read units of said number of said read units includes (i) one or more headers and (ii) a portion of said compressed data. ### Claim 13 An apparatus comprising: a nonvolatile memory; and a circuit configured to (i) receive a read request from a host to read particular data corresponding to a logical block address from said nonvolatile memory, (ii) read a particular one of a plurality of entries in a map to obtain (a) a physical address of a particular one of a plurality of pages of said nonvolatile memory, (b) an offset in said particular page to compressed data previously stored in response to writing said compressed data corresponding to said logical block address and (c) a length of said compressed data, wherein said particular entry is associated with said logical block address, (iii) convert said offset and said length to (a) an address of a given one of a plurality of read units in said particular page and (b) a number of said read units to be read from said particular page and (iv) read from said particular page at most said number of said read units starting from said given read unit, wherein a granularity of said offset and said length is finer than a size of one of said read units. ### Claim 14 (depends on 13) The apparatus according to claim 13, wherein said circuit is further configured to (i) perform error correction decoding on each of said read units as read from said particular page to generate corrected data and (ii) extract said compressed data from said corrected data according to both (a) said offset in said particular page to said compressed data and (b) said length of said compressed data. ### Claim 15 (depends on 14) The apparatus according to claim 14, wherein said circuit is further configured to (i) decompress said compressed data to generate return data and (ii) transfer said return data to said host. ### Claim 16 (depends on 13) The apparatus according to claim 13, wherein said number of said read units to be read is less than all of said read units in said particular page. ### Claim 17 (depends on 13) The apparatus according to claim 13, wherein said circuit is further configured to determine that at least a portion of said compressed data is in one or more subsequent read units of a subsequent one of said pages of said nonvolatile memory based on both (i) said offset in said particular page to said compressed data and (ii) said length of said compressed data combined with an amount of user data in said particular page. ### Claim 18 (depends on 17) The apparatus according to claim 17, wherein said circuit is further configured to read from said subsequent page at most said one or more subsequent read units. ### Claim 19 (depends on 13) The apparatus according to claim 13, wherein (i) a first one of said pages of said nonvolatile memory includes a first number of said read units, (ii) a second one of said pages of said nonvolatile memory includes a second number of said read units and (iii) said first number is different from said second number. ### Claim 20 (depends on 13) The apparatus according to claim 13, wherein said apparatus is implemented as one or more integrated circuits.