# US 2014/0207994 A1 · Circuit arrangement for universal connection of a bus participant to at least one bus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0207994 A1 - Document ID: US20140207994A1 - Status: Published application - Kind: A1 - Application number: 14/161,064 - Filed: 2014-01-22 - Published: 2014-07-24 - Earliest claimed: 2013-01-22 - Assignees: dSPACE digital signal processing and control engineering GmbH - Applicants: dSPACE digital signal processing and control engineering GmbH - Inventors: Abdallah CHERKAOUI; Christian DIERKES; Lars KOPKA - Web page: https://patentgrep.com/patent/US20140207994A1 ## CPC - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - H04L 12/40032: {Details regarding a bus interface enhancer} - H04L 12/40169: {Flexible bus arrangements (arrangements for maintenance or administration involving management of faults; events, alarms H04L41/06; automatic restoration of network faults H04L41/0654)} - H04L 12/42: Loop networks - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A circuit arrangement for connecting a bus participant to at least one bus, having an interface for connecting the bus participant to the circuit arrangement, a first bus input, and a first bus output between which the bus participant is switchable via the interface. The circuit arrangement includes a second bus input and output for connecting the bus to the circuit arrangement in a ring topology in such a way that the first bus output is connected at least indirectly to the second bus input and the second bus output is connected at least indirectly to the first bus input via the bus. The bus in the circuit arrangement can be separated to obtain a line topology and can be configured as bus-terminating at one of the bus inputs or bus outputs. A system for the functional testing of bus participants on a bus in a simulation environment is provided. ## Claims ### Claim 1 A circuit arrangement for connecting a bus participant to at least one bus, the circuit arrangement comprising: an interface for connecting the bus participant to the circuit arrangement; a first bus input and a first bus output, between which the bus participant is switchable via the interface; and a second bus input and a second bus output for connecting the bus to the circuit arrangement in a ring topology such that the first bus output is connected at least indirectly to the second bus input via the bus and the second bus output is connected at least indirectly to the first bus input via the bus, wherein the bus in the circuit arrangement is configured to be separated to obtain a line topology, and wherein the circuit arrangement is configured as bus-terminating at one of the bus inputs or bus outputs. ### Claim 2 (depends on 1) The circuit arrangement according to claim 1, wherein the interface is connectable via a first switch group to the first bus input and the first bus output or the second bus input and the second bus output, and wherein the connection from the first switch group to the second bus input and to the second bus output is severable by a disconnect switch group in order to change the ring topology of the bus to a line topology. ### Claim 3 (depends on 2) The circuit arrangement according to claim 2, further comprising a termination unit for the electrical termination of the bus, which, depending on a position of the disconnect switch group, is connectable to the second bus input and/or the second bus output via at least one termination switch. ### Claim 4 (depends on 2) The circuit arrangement according to claim 2, wherein the disconnect switch groups comprise double-throw switches and selectively connect the second bus input and/or the second bus output to the first switch group or to a bypass line. ### Claim 5 (depends on 1) The circuit arrangement according to claim 1, further comprising a bridging switch group for direct connection of the first bus input to the first bus output. ### Claim 6 (depends on 1) The circuit arrangement according to claim 1, wherein the interface is connectable to the first switch group via an activation switch group for coupling and decoupling the bus participant to or from the bus. ### Claim 7 (depends on 6) The circuit arrangement according to claim 6, wherein the activation switch group has a switch pair for each line of the bus, and wherein the switch pairs are switchable independently of one another. ### Claim 8 (depends on 1) The circuit arrangement according to claim 1, wherein the circuit arrangement is adapted to be connected to a second bus, particularly a second CAN bus, and further comprises a bus changeover switch group via which the interface is selectively connectable to the first bus or to the second bus. ### Claim 9 (depends on 8) The circuit arrangement according to claim 8, wherein the second bus comprises a first bus input, a first bus output, a second bus input, and a second bus output such that the second bus is placeable in a ring topology such that the first bus output is connected at least indirectly to the second bus input via the second bus and the second bus output is connected at least indirectly to the first bus input via the second bus. ### Claim 10 (depends on 8) The circuit arrangement according to claim 8, further comprising a second switch group via which the interface in the position selecting the second bus of the bus changeover switch group is selectively connectable to the first bus input and the first bus output or to the second bus input and the second bus output of the second bus. ### Claim 11 (depends on 10) The circuit arrangement according to claim 10, wherein the connection from the second switch group to the second bus input and to the second bus output of the second bus is adapted to be severed in each case by a disconnect switch group in order to change the ring topology of the second bus to a line topology, and further comprising a second termination unit for the electrical termination of the second bus, which, depending on the position of the disconnect switch groups, is connectable to the second bus input or the second bus output via at least one termination switch. ### Claim 12 (depends on 11) The circuit arrangement according to claim 11, wherein the disconnect switch groups each comprise double-throw switches and the second bus input and/or connect the second bus output of the second bus selectively to the second switch group or to another bypass line (16). ### Claim 13 (depends on 1) The circuit arrangement according to claim 1, further comprising a bridging switch group for the direct connection of the first bus input to the first bus output of the first bus and/or a bridging switch group for the direct connection of the first bus input to a first bus output of a second bus. ### Claim 14 (depends on 1) The circuit arrangement according to claim 1, wherein the first and/or a second bus are realized as dual-wire, and wherein a first switch group and/or a second switch group and a disconnect switch groups each comprise a switch for each of the two bus lines. ### Claim 15 (depends on 3) The circuit arrangement according to claim 3, wherein the termination unit and/or a second termination unit are formed by a termination resistor, which is switchable via a respective termination switch between the lines of the respective bus. ### Claim 16 (depends on 3) The circuit arrangement according to claim 3, wherein the termination unit and/or a second termination unit are formed by two termination resistors, which together are connected to a ground via a capacitor, and wherein the one termination resistor is connectable to one of the bus lines via a termination switch and the other termination resistor to the other bus line via another termination switch. ### Claim 17 A system for the functional testing of bus participants on a bus in a simulation environment, the system comprising: a plurality of circuit arrangements; and a bus, wherein the bus participants are each connectable to the bus via one of the circuit arrangements; and a simulator unit for simulating control signals on the bus, wherein each of the circuit arrangements has a first and a second bus input and a first and a second bus output and the bus connects the circuit arrangements in a ring topology such that each first bus output of one of the circuit arrangements is connectable either to the first bus input of the next circuit arrangement or to the second bus input of its own circuit arrangement, wherein each second bus output of one of the circuit arrangements is connectable either to the second bus input of the next circuit arrangement or to the first bus input of its own circuit arrangement, and wherein the bus in each of the circuit arrangements is separated to obtain a line topology and each circuit arrangement is configured as bus-terminating at one of the bus inputs or bus outputs. ### Claim 18 (depends on 17) The system according to claim 17, further comprising a second bus, which connects the circuit arrangements in the same way as the first bus. ### Claim 19 (depends on 17) The system according to claim 17, wherein each of the circuit arrangements comprises: an interface for connecting the bus participant to the circuit arrangement; a first bus input and a first bus output, between which the bus participant is switchable via the interface; and a second bus input and a second bus output for connecting the bus to the circuit arrangement in a ring topology such that the first bus output is connected at least indirectly to the second bus input via the bus and the second bus output is connected at least indirectly to the first bus input via the bus, wherein the bus in the circuit arrangement is configured to be separated to obtain a line topology, and wherein the circuit arrangement is configured as bus-terminating at one of the bus inputs or bus outputs. ### Claim 20 (depends on 1) The circuit arrangement according to claim 1, wherein the bus is a CAN bus.