# US 2014/0207992 A1 · Processor with tightly coupled smart memory unit

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- Number: US 2014/0207992 A1
- Document ID: US20140207992A1
- Status: Published application
- Kind: A1
- Application number: 14/220,735
- Filed: 2014-03-20
- Published: 2014-07-24
- Earliest claimed: 2010-11-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shyh-An CHI
- Web page: https://patentgrep.com/patent/US20140207992A1

## CPC

- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA]
- G06F 13/24: using interrupt (G06F13/32 takes precedence)
- G06F 13/32: using combination of interrupt and burst mode transfer
- G06F 13/4063: {Device-to-bus coupling}
- G06F 15/7821: {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory}
- G06F 2212/2532: comprising a plurality of modules
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An information processor includes a central processing unit core and a direct memory access unit connected to the central processing unit core. The information processor further includes at least one tightly coupled smart memory unit connected to the central processing unit core. The at least one tightly coupled smart memory unit includes a memory unit, and a local processing unit adapted to process data stored in the memory unit, wherein the memory unit is adapted to be accessed by the central processing unit core and the local processing unit, and the local processing unit is separate from the central processing unit core and the direct memory access unit.

## Claims

### Claim 1

An information processor comprising:
a central processing unit core;
a direct memory access unit connected to the central processing unit core; and
at least one tightly coupled smart memory unit connected to the central processing unit core, the at least one tightly coupled smart memory unit comprising:
a memory unit;
a local processing unit adapted to process data stored in the memory unit, wherein the memory unit is adapted to be accessed by the central processing unit core and the local processing unit, and the local processing unit is separate from the central processing unit core and the direct memory access unit.

### Claim 2 (depends on 1)

The information processor of claim 1, wherein the central processing unit core is connected to the at least one tightly coupled memory unit via a bi-directional bus.

### Claim 3 (depends on 1)

The information processor of claim 1, wherein the direct memory access unit is for transferring data to the memory unit, and is configured to generate an interrupt of the central processing unit upon completion of transferring the data.

### Claim 4 (depends on 1)

The information processor of claim 1, wherein the at least one tightly coupled smart memory unit further comprises control and status registers configured to receive operation instructions from the central processing unit core.

### Claim 5 (depends on 4)

The information processor of claim 4, wherein the control and status registers are further configured to control the local processing unit based on received operation instructions.

### Claim 6 (depends on 4)

The information processor of claim 4, wherein the local processing unit is configured to update the control and status registers.

### Claim 7 (depends on 6)

The information processor of claim 6, wherein the control and status registers are further configured to generate an interrupt of the central processing unit core.

### Claim 8 (depends on 1)

The information processor of claim 1, wherein the local processing unit is reprogrammable.

### Claim 9 (depends on 1)

The information processor of claim 1, wherein the central processing unit core is connected to the local processing unit via a bi-directional bus.

### Claim 10 (depends on 1)

The information processor of claim 1, wherein the memory unit is a dual port memory unit, the central processing unit core is connected to the dual port memory unit via a bi-directional bus, and the dual port memory unit is between the bi-directional bus and the local processing unit.

### Claim 11 (depends on 1)

The information processor of claim 1, wherein the at least one tightly coupled smart memory unit further comprises:
a second memory unit; and
a second local processing unit, wherein the second local processing unit is separate from the local processing unit and the central processing unit core.

### Claim 12

An information processor comprising:
a central processing unit core; and
at least one tightly coupled smart memory unit connected to the central processing unit core, the at least one tightly coupled smart memory unit comprising:
a plurality of memory units;
a plurality of local processing units;
a plurality of registers adapted to be accessed by the central processing unit core and the plurality of local processing units,
wherein each local processing unit of the plurality of local processing units is adapted to process data stored in a corresponding memory unit of the plurality of memory units or a corresponding register of the plurality of registers,
wherein each memory unit of the plurality of memory units is adapted to be accessed by the central processing unit core and a corresponding local processing unit of the plurality of local processing units,
wherein each local processing unit of the plurality of local processing units is configured to receive instructions from the central processing unit core or a register of the plurality of registers.

### Claim 13 (depends on 12)

The information processor of claim 12, wherein each local processing unit of the plurality of local processing units is configured to receive instructions directly from the central processing unit core.

### Claim 14 (depends on 12)

The information processor of claim 12, wherein at least one memory unit of the plurality of memory units is a dual port memory unit.

### Claim 15 (depends on 12)

The information processor of claim 12, wherein at least one memory unit of the plurality of memory units is configured to be simultaneously accessed by the central processing unit core and by a corresponding local processing unit of the plurality of local processing units.

### Claim 16 (depends on 12)

The information processor of claim 12, wherein a first local processing unit of the plurality of local processing units is configured to exchange data with a second local processing unit of the plurality of local processing units.

### Claim 17 (depends on 12)

The information processor of claim 12, wherein each memory unit of the plurality of memory units is connected to the central processing unit core by a bi-directional bus.

### Claim 18 (depends on 12)

The information processor of claim 12, further comprising a direct memory access unit connected to the central processing unit core, wherein the direct memory access unit is separate from the tightly coupled smart memory unit.

### Claim 19

An information processor comprising:
a central processing unit core;
a direct memory access unit connected to the central processing unit core; and
at least one tightly coupled smart memory unit connected to the central processing unit core and to the direct memory access unit by a bi-directional bus, the at least one tightly coupled smart memory unit comprising:
a dual port memory unit;
a local processing unit adapted to process data stored in the dual port memory unit, wherein the dual port memory unit is adapted to be accessed by the central processing unit core and the local processing unit, and the local processing unit is separate from the central processing unit core and the direct memory access unit.

### Claim 20 (depends on 19)

The information processor of claim 19, wherein the at least one tightly coupled smart memory unit further comprises control and status registers configured to receive operation instructions from the central processing unit core and to control the local processing unit.