# US 2014/0207983 A1 · Time-division multiplexed data bus interface

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- Number: US 2014/0207983 A1
- Document ID: US20140207983A1
- Status: Published application
- Kind: A1
- Application number: 13/747,205
- Filed: 2013-01-22
- Published: 2014-07-24
- Earliest claimed: 2013-01-22
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Girault W. Jones; Nathan A. Johanningsmeier; Casey L. Hardy
- Web page: https://patentgrep.com/patent/US20140207983A1

## CPC

- G06F 13/4291: {using a clocked protocol}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An audio system bus has a bus data line and a bus clock line. Audio producers are coupled to the bus to form a time-division multiplexed multi drop bus interface arrangement having protocol slots 0,1, . . . N where N is an integer greater than two. A bus device is coupled to the bus that produces a) a frame marker on the bus data line in slot 0, and b) a data bit on the bus data line in slot 1. The audio producers are to produce their respective audio data bits in their assigned slots other than slots 0 and 1. Other embodiments are also described and claimed.

## Claims

### Claim 1

A method for performing a time-division multiplexed data bus protocol having successive time slots 0, 1, 2, . . . N in each frame interval, where N is an integer greater than two, the method comprising
the following operations performed over a plurality of frame intervals, by a first bus device and a second bus device that are coupled to a bus data line:
driving a frame marker on the bus data line by the first bus device in slot 0, wherein the frame marker has a plurality of framer marker bits each being driven by the first bus device in a respective instance of slot 0 in the frame intervals;
driving the bus data line with first device data in slot 1, by the first bus device; and
driving the bus data line with second device data in an assigned slot other than slots 0 and 1, by the second bus device.

### Claim 2 (depends on 1)

The method of claim 1 wherein driving the bus data line by the first bus device comprises:
driving each one of a plurality of data bits in a respective instance of slot 1 in a plurality of frame intervals, respectively, wherein the first bus device presents essentially an open circuit to the bus data line between slot 1 until the next instance of slot 0.

### Claim 3 (depends on 1)

The method of claim 1 wherein driving the bus data line by the second bus device comprises:
the second bus device driving each one of a plurality of data bits in a respective instance of its assigned slot in a plurality of frame intervals, respectively, wherein the second bus device presents essentially an open circuit to the bus data line between its assigned slot until the next instance of its assigned slot.

### Claim 4 (depends on 1)

The method of claim 1 wherein the bus data line remains essentially floating while no bus devices are driving the bus data line.

### Claim 5 (depends on 3)

The method of claim 3 wherein each bit consists of a single binary logic bit.

### Claim 6 (depends on 5)

The method of claim 5 wherein driving the bus data line by the second bus device comprises:
driving the plurality of data bits in accordance with pulse density modulation, one binary logic bit per instance of the assigned slot.

### Claim 7 (depends on 1)

The method of claim 1 wherein each slot is coextensive with a half-cycle of a clock signal, and wherein each frame interval has a fixed length of (N+1)/2 cycles of the clock signal.

### Claim 8 (depends on 2)

The method of claim 2 wherein the plurality of data bits driven by the first bus device are one of a) an audio stream, b) a command or control word and c) dummy data.

### Claim 9

A time-division multiplexed data bus device comprising:
a first modulator to receive a first data signal; and
a first bus interface circuit having
a multiplexor with a control input that is to receive a select signal synchronized with a clock signal,
a frame marker generation circuit coupled to an input of the first multiplexor and responsive to the clock signal, wherein another input of multiplexor is coupled to an output of the first modulator,
a switch circuit with a) an input coupled to an output of the first multiplexor and b) an output to be coupled to a bus data line, and
a switch controller coupled to control the switch circuit responsive to the clock signal so that the switch circuit is enabled during slots 0 and 1 of a time-division multiplexed data bus protocol having successive time slots 0, 1, 2, . . . N in each frame interval, where N is an integer greater than two.

### Claim 10 (depends on 9)

The data bus device of claim 9 in combination with a further data bus device that comprises:
a second modulator to receive a second data signal; and
a second bus interface circuit having
frame synchronization logic responsive to the clock signal and having an input to be coupled to the bus data line, to detect a frame marker,
a switch circuit with a) an input coupled to an output of the second modulator and b) an output to be coupled to the bus data line, and
a switch controller coupled to control the switch circuit responsive to the clock signal and the frame synch logic so that the switch circuit is enabled during an assigned slot other than slots 0 and 1 of the time-division multiplexed data bus protocol.

### Claim 11 (depends on 10)

The data bus devices of claim 10 wherein the frame marker generation circuit in the first bus interface circuit and the frame synch logic in the second bus interface circuit each comprise a LFSR circuit that is responsive to the clock signal.

### Claim 12 (depends on 9)

The data bus device of claim 9 wherein the first bus interface circuit is to drive each one of a plurality of data bits from the first modulator in a respective instance of slot 1 in a plurality of frame intervals, respectively, and is to present essentially an open circuit to the bus data line between slot 1 until the next instance of slot 0.

### Claim 13 (depends on 10)

The data bus devices of claim 10 wherein the second bus interface circuit is to drive each one of a plurality of data bits from the second modulator in a respective instance of its assigned slot in a plurality of frame intervals, respectively, and is to present essentially an open circuit to the bus data line between its assigned slot in a given frame interval until the next instance of its assigned slot in a subsequent frame interval.

### Claim 14 (depends on 9)

The data bus device of claim 9 further comprising a microphonic sensor, wherein the modulator comprises an analog to digital converter that is to receive the first data signal being an analog signal from the sensor.

### Claim 15 (depends on 9)

The data bus device of claim 9 wherein the switch circuit comprises a tri-state buffer.

### Claim 16

A time-division multiplexed data bus device, comprising:
a bus interface circuit having
a multiplexor with a control input that is to receive a select signal synchronized with a clock signal, a frame marker generation circuit coupled to an input of the first multiplexor and responsive to the clock signal, wherein another input of multiplexor is coupled to receive a data signal, a switch circuit with a) an input coupled to an output of the first multiplexor and b) an output to be coupled to a bus data line, and a switch controller coupled to control the switch circuit responsive to the clock signal so that the switch circuit is enabled during slots 0 and 1 of a time-division multiplexed data bus protocol having successive time slots 0, 1, 2, . . . N in each frame interval, where N is an integer greater than two; and
a demultiplexor having an input coupled to the bus data line and a plurality of outputs each to produce a bitstream for a respective channel, controller logic to receive the clock signal and a frame marker produced by the frame marker generation circuit and having an output coupled to a control input of the demultiplexor.

### Claim 17 (depends on 16)

The bus device of claim 16 wherein the bus interface circuit further comprises a clock generator that produces the clock signal.

### Claim 18

A multi-channel audio system comprising:
a bus having a bus data line and a bus clock line;
a plurality of microphone circuits each having a respective audio pick-up device and a respective bus interface circuit that is coupled to the bus to form a time-division multiplexed multi-drop bus interface arrangement having protocol slots 0, 1, . . . N where N is an integer greater than two; and
a bus device that is to produce a) a frame marker on the bus data line in slot 0, wherein the frame marker has a plurality of framer marker bits each to be driven by the bus device in a respective instance of slot 0, and b) a data bitstream on the bus data line in slot 1,
wherein the respective bus interface circuit of each of the plurality of microphone circuits is coupled to the bus clock line to receive a clock and to use the clock to detect the frame marker on the bus data line, and in response to having detected the frame marker drive a respective audio bitstream in its assigned protocol slot.

### Claim 19 (depends on 18)

The audio system of claim 18 wherein each bit consists of a single binary logic bit.

### Claim 20 (depends on 18)

The audio system of claim 18 wherein the bus device that produces the frame marker further comprises a circuit that produces the clock on the bus clock line.

### Claim 21 (depends on 18)

The audio system of claim 18 wherein the bus device that produces the frame marker further comprises an audio pick-up device, and wherein the data bitstream produced by the bus device in slot 1 is from a signal sensed by the audio pick-up device.

### Claim 22 (depends on 18)

The audio system of claim 18 wherein the bus data line is essentially floating when it is not being pulled up or pulled down by any of the audio producers.