# US 2014/0207982 A1 · Signal Processing System and Method for Processing Signals in a Bus Node > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0207982 A1 - Document ID: US20140207982A1 - Status: Published application - Kind: A1 - Application number: 14/119,094 - Filed: 2012-07-06 - Published: 2014-07-24 - Earliest claimed: 2011-07-06 - Assignees: Festo AG & Co. - Inventors: Uwe Graff - Web page: https://patentgrep.com/patent/US20140207982A1 ## CPC - G06F 13/1652: {in a multiprocessor architecture (interprocessor communication using common memory G06F15/167)} - G06F 13/40: Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} - H04L 12/40006: {Architecture of a communication node (current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90)} - H04L 12/40032: {Details regarding a bus interface enhancer} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A signal processing system having a bus node, which is designed for signal conversion between signals of an internal and an external bus system and in each case includes at least one interface to be coupled to the external bus system and to the internal bus system, and having at least one signal conditioning module, which is designed for physical conditioning and/or analog/digital conversion for signals from an external component and includes an interface for an internal bus system and at least one connection for the external component and is connected to the bus note via the internal bus system. The bus node is designed for internal raw data processing of the signals provided by the signal conditioning module and to output at least one output signal dependent on the processed signals to the internal and/or to the external bus system. ## Claims ### Claim 1 A signal processing system with a bus node, which is designed for signal conversion between signals of an internal and an external bus system, and in each case comprising at least one interface for coupling to the external bus system and the internal bus system, and with at least one signal conditioning module which is designed for physical conditioning and/or analog-to-digital conversion of signals of an external component and has an interface for the internal bus system and at least one connection for the external component, and is connected to the bus node via the internal bus system, wherein the bus node is designed for internal raw data processing of signals provided by the signal conditioning module, and for output of at least one output signal, dependent on the processed signals, to the internal and/or the external bus system. ### Claim 2 (depends on 1) A signal processing system according to claim 1, wherein the bus node includes an at least partly freely programmable and/or freely allocable memory device for the storage of an algorithm, and a processing device for processing the signals provided by the signal conditioning module and for the output of an output signal by means of the stored algorithm. ### Claim 3 (depends on 2) A signal processing system according to claim 2, wherein the processing device contains several instruction levels for the processing of different instructions, wherein a first instruction level is set up for direct communication with the processing device, and further instruction levels for exclusive communication with in each case adjacent instruction levels. ### Claim 4 (depends on 3) A signal processing system according to claim 3, wherein the processing device is set up in one instruction level, located above the first instruction level, for the operation of one more instruction modules preferably presettable by the end user, and wherein the algorithm provided for processing the signals supplied from the signal conditioning module and to output an output signal is in the form of an instruction module. ### Claim 5 (depends on 3) A signal processing system according to claim 3, wherein the processing device is set up, in an instruction level which is located above the first instruction level, for data interchange with at least one instruction module by means of a standardised instruction command set. ### Claim 6 (depends on 5) A signal processing system according to claim 5, wherein the processing device includes in one instruction level, which is located above the first instruction level, a virtual machine which is designed to operate the instruction module in a standardized instruction module environment. ### Claim 7 (depends on 5) A signal processing system according to claim 5, wherein the virtual machine is set up for simultaneous administration of several instruction modules and/or wherein several virtual machines are provided for the processing of different instruction modules. ### Claim 8 (depends on 2) A signal processing system according to claim 2, wherein the memory device is designed for write access or read-write access on the instruction module or modules by means of the external bus system and/or an input interface formed on the bus node, in order to facilitate modification and/or parameter setting and/or replacement of the instruction module. ### Claim 9 (depends on 4) A signal processing system according to claim 4, wherein the instruction module is designed for monitoring energy flows and/or volume flows and/or servicing intervals and/or safety functions of the external components connected thereto. ### Claim 10 (depends on 1) A signal processing system according to claim 1, wherein the signal conditioning module is designed exclusively for physical conditioning and/or analog-to-digital conversion of signals of one external component. ### Claim 11 (depends on 1) A signal processing system according to claim 1, wherein the bus node is designed for the provision of an output signal which is set up for the driving of at least one external component and/or function module connected to a signal conditioning module. ### Claim 12 A method for processing signals in a signal processing system which is designed for detection of signals of an external component, passing on of the signals via an internal bus system to a bus nodes and processing of the signals in the bus node the method comprising receiving of signals from an external component, conditioning and or digitalisation of the signals, transmission of the signals via the internal bus system to the bus node, processing of the signals arriving as raw data in the bus node by means of an algorithm filed in the bus node, output of an output signal generated through the processing to an external component and/or a function module. ### Claim 13 (depends on 12) A method according to claim 12, wherein the signals arriving at the bus node as raw data are processed in a processing device included in the bus node and in which several instruction levels are designed for the processing of several instructions, wherein a first instruction level is set up for direct communication with the processing device and further instruction levels for communication with respectively adjacent instruction levels, in a further instruction level located above the first instruction level by the algorithm in the form of an instruction module, in a virtual machine. ### Claim 14 (depends on 12) A method according to claim 12, wherein write access or read-write access to the memory device is made by means of the external bus system and/or an input interface formed at the bus node, in order to accomplish a change and/or parameter setting and/or replacement of the instruction module. ### Claim 15 (depends on 12) A method according to claim 12, wherein the signal conditioning module carries out exclusively physical conditioning and/or analog-to-digital conversion of signals of an external component.