# US 2014/0198157 A1 · Process for producing chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0198157 A1 - Document ID: US20140198157A1 - Status: Published application - Kind: A1 - Application number: 14/146,203 - Filed: 2014-01-02 - Published: 2014-07-17 - Earliest claimed: 2013-01-11 - Assignees: Canon Kabushiki Kaisha - Applicants: Canon Kabushiki Kaisha - Inventors: Keiji Tomizawa; Chiaki Muraoka; Takuma Kodoi - Web page: https://patentgrep.com/patent/US20140198157A1 ## CPC - B41J 2/1631: {photolithography} - B41J 2/145: Arrangement thereof - B41J 2/15: for serial printing - B41J 2/1601: {Production of bubble jet print heads (B41J2/1606, B41J2/162 take precedence)} - B41J 2/1635: {dividing the wafer into individual chips} - B41J 2/1639: {sacrificial molding} - B41J 2/1645: {thin film formation by spincoating} - B41J: TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS ## Abstract A process for producing a chip in which plural ejection orifice arrays are arranged including conducting reduction projection exposure plural times to a wafer having a substrate and a photosensitive resin layer formed thereon while relatively moving positions of the wafer and a reticle to form ejection orifice array patterns in the resin layer, developing the patterns to form ejection orifice arrays in the resin layer, and dividing the wafer to form plural chips in which the plural ejection orifice arrays are arranged. The exposure is conducted once to form in the resin layer a first ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip, a second ejection orifice array pattern corresponding to all ejection orifice arrays in one chip and a third ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip. ## Claims ### Claim 1 A process for producing a chip in which plural ejection orifice arrays are arranged, the process comprising the steps of: conducting reduction projection exposure plural times to a wafer having a substrate and a photosensitive resin layer formed on the substrate while relatively moving positions of the wafer and a reticle to form ejection orifice array patterns in the photosensitive resin layer, developing the ejection orifice array patterns to form ejection orifice arrays in the photosensitive resin layer, and dividing the wafer having the photosensitive resin layer in which the ejection orifice arrays have been formed to form plural chips in which the plural ejection orifice arrays are arranged, wherein the reduction projection exposure is conducted once to form in the photosensitive resin layer a first ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction of ejection orifice arrays in one chip, a second ejection orifice array pattern corresponding to all ejection orifice arrays in another one chip and a third ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction of ejection orifice arrays in a further one chip. ### Claim 2 (depends on 1) The process according to claim 1, wherein an ejection orifice array pattern corresponding to all ejection orifice arrays in one chip is formed by the first ejection orifice array pattern formed by one exposure and a third ejection orifice array pattern formed by next one exposure conducted after positions of the wafer and the reticle are relatively moved. ### Claim 3 (depends on 1) The process according to claim 1, wherein the first ejection orifice array pattern and the third ejection orifice array pattern have an ejection orifice array pattern corresponding to half of all ejection orifice arrays in one chip. ### Claim 4 (depends on 1) The process according to claim 1, wherein the second ejection orifice array pattern has an ejection orifice array pattern corresponding to three or more ejection orifice arrays, and the three or more ejection orifice arrays include ejection orifice arrays for respectively ejecting liquids of different colors, and the ejection orifice arrays are arranged in such a manner that the color arrangement of the liquids becomes line symmetry when viewed from an ejection orifice array located at the center. ### Claim 5 (depends on 4) The process according to claim 4, wherein the three or more ejection orifice arrays have an ejection orifice array (C) for ejecting a cyan ink, an ejection orifice array (M) for ejecting a magenta ink and an ejection orifice array (Y) for ejecting a yellow ink, and the chip is constituted in such a manner that the ejection orifice arrays are arranged in the order of CMYMC. ### Claim 6 (depends on 5) The process according to claim 5, wherein the ejection orifice array (C) for ejecting the cyan ink, the ejection orifice array (M) for ejecting the magenta ink and the ejection orifice array (Y) for ejecting the yellow ink are each constituted by two ejection orifice arrays. ### Claim 7 A chip in which plural ejection orifice arrays are arranged, wherein the length of a central ejection orifice array among ejection orifice arrays constituting the plural ejection orifice arrays is longest, and the ejection orifice arrays are arranged in descending order of the length of the ejection orifice array from the central ejection orifice array toward ejection orifice arrays on both sides. ### Claim 8 A chip in which plural ejection orifice arrays are arranged, wherein the length of a central ejection orifice array among ejection orifice arrays constituting the plural ejection orifice arrays is shortest, and the ejection orifice arrays are arranged in ascending order of the length of the ejection orifice array from the central ejection orifice array toward ejection orifice arrays on both sides. ### Claim 9 (depends on 7) The chip according to claim 7, wherein the plural ejection orifice arrays include ejection orifice arrays for respectively ejecting liquids of different colors, and the ejection orifice arrays are arranged in such a manner that the color arrangement of the liquids becomes line symmetry when viewed from the central ejection orifice array. ### Claim 10 (depends on 8) The chip according to claim 8, wherein the plural ejection orifice arrays include ejection orifice arrays for respectively ejecting liquids of different colors, and the ejection orifice arrays are arranged in such a manner that the color arrangement of the liquids becomes line symmetry when viewed from the central ejection orifice array.