# US 2014/0198138 A1 · Low power display device with variable refresh rates > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0198138 A1 - Document ID: US20140198138A1 - Status: Published application - Kind: A1 - Application number: 14/155,297 - Filed: 2014-01-14 - Published: 2014-07-17 - Earliest claimed: 2013-01-14 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Prasanna Nambi; Jason N. Gomez; Fenghua Zheng; Paolo Sacchetto; Sandro H. Pintz; Taesung Kim; Christopher P. Tann; Marc Albrecht; David W. Lum - Web page: https://patentgrep.com/patent/US20140198138A1 ## CPC - G09G 3/3618: {with automatic refresh of the display panel using sense/write circuits} - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G09G 3/36: using liquid crystals - G09G 3/3611: {Control of matrices with row and column drivers} - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G09G 3/3696: {Generation of voltages supplied to electrode drivers} - G06T 2210/52: Parallel processing - G09G 3/3655: {Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors} - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0626: for control of overall brightness - G09G 2330/02: Details of power systems and of start or stop of display operation - G09G 2330/021: Power management, e.g. power saving - G09G 2340/0435: Change or adaptation of the frame rate of the video stream - G09G 2360/18: Use of a frame buffer in a display terminal, inclusive of the display panel - G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below. ## Claims ### Claim 1 A method of compensating for an image presentation deficiency at a liquid crystal display (LCD), the method comprising: at a buffer circuit, receiving a reference voltage input selection; at the buffer circuit, comparing the reference voltage input selection to a plurality of preloaded register values; and at the buffer circuit, selecting a target reference voltage value based on the comparison of the reference voltage input selection to the plurality of preloaded register values to affect a change in luminosity of the LCD. ### Claim 2 (depends on 1) The method of claim 1, wherein the image presentation deficiency is associated with an altered luminosity level of the LCD that is caused by employing a variable refresh rate at the LCD. ### Claim 3 (depends on 1) The method of claim 1, wherein the reference voltage input selection is received at a dedicated hardware pin of the buffer circuit from a display timing controller. ### Claim 4 (depends on 1) The method of claim 1, wherein the reference voltage input selection is received in response to an identification of the image presentation deficiency. ### Claim 5 (depends on 4) The method of claim 4, wherein the image presentation deficiency is identified at the buffer circuit or at a graphics processor unit (GPU) that is configured to drive the LCD. ### Claim 6 (depends on 4) The method of claim 4, wherein the identification of the image processing deficiency corresponds to a detection of a reduced refresh rate employed by the LCD. ### Claim 7 (depends on 1) The method of claim 1, wherein the target reference voltage value is selected to increase a luminosity of the LCD when the LCD is operating at a reduced refresh rate. ### Claim 8 (depends on 1) The method of claim 1, wherein the target reference voltage value is selected to decrease a luminosity of the LCD when the LCD is operating at an increased refresh rate. ### Claim 9 A buffer circuit of a liquid crystal display (LCD), comprising: a reference voltage bank selection component storing a plurality of register values; a plurality of operational amplifiers; and a plurality of image buffers, wherein the buffer circuit is configured to: receive a reference voltage input selection; compare the reference voltage input selection to the plurality of register values; select a target reference voltage value based on the comparison; and transmit the target reference voltage value to the LCD to change a luminosity of the LCD when the LCD is operating at a reduced refresh rate. ### Claim 10 (depends on 9) The buffer circuit of claim 9, wherein the reference voltage input selection is received at a dedicated hardware pin of the buffer circuit from a display timing controller. ### Claim 11 (depends on 9) The buffer circuit of claim 9, wherein: the reference voltage input selection is received in response to an identification of an image presentation deficiency; and the image presentation deficiency is associated with one or more undesirable image artifacts or an altered image luminosity. ### Claim 12 (depends on 11) The buffer circuit of claim 11, wherein the image presentation deficiency is identified at the buffer circuit or at a graphics processor unit (GPU) that is configured to drive the LCD. ### Claim 13 (depends on 11) The buffer circuit of claim 11, wherein the identification of the image processing deficiency corresponds to a detection of a reduced refresh rate employed by the LCD. ### Claim 14 (depends on 9) The buffer circuit of claim 9, wherein the target reference voltage value is selected to increase a luminosity of the LCD when the LCD is operating at a reduced refresh rate or to decrease a luminosity of the LCD when the LCD is operating at an increased refresh rate. ### Claim 15 A method of compensating for an image presentation deficiency at a liquid crystal display (LCD), the method comprising: at a buffer circuit, selecting a target reference voltage value from a plurality of register values; at the buffer circuit, synchronizing a counter clock signal with an input from a display timing controller; at the buffer circuit, selecting a slope setting based on the target reference voltage value and the synchronized counter clock signal; and at the buffer circuit, applying the slope setting to affect a gradual transition from a current reference voltage output to a target reference voltage output. ### Claim 16 (depends on 15) The method of claim 15, wherein the target reference voltage output corresponds to a voltage value that is equal to the target reference voltage value. ### Claim 17 (depends on 15) The method of claim 15, wherein the gradual transition from the current reference voltage output to the target reference voltage output results in a visual presentation at the LCD that is free from perceptible image presentation artifacts caused by the transition. ### Claim 18 (depends on 17) The method of claim 17, wherein the gradual transition from the current reference voltage output to the target reference voltage output corresponds to a transition between a first refresh rate and a second refresh rate being employed by the LCD. ### Claim 19 (depends on 18) The method of claim 18, wherein the first refresh rate is larger than the second refresh rate and the second refresh rate is configured to cause the LCD to conserve power. ### Claim 20 (depends on 15) The method of claim 15, wherein application of the slope setting causes the target reference voltage output to track a direction of the synchronized counter clock signal.