# US 2014/0198116 A1 · A method and device to augment volatile memory in a graphics subsystem with non-volatile memory

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- Number: US 2014/0198116 A1
- Document ID: US20140198116A1
- Status: Published application
- Kind: A1
- Application number: 13/977,261
- Filed: 2011-12-28
- Published: 2014-07-17
- Earliest claimed: 2011-12-28
- Assignees: Intel Corporation
- Inventors: Bryan E. Veal; Travis T. Schluessler; Murali Ramadoss; Balaji Vembu
- Web page: https://patentgrep.com/patent/US20140198116A1

## CPC

- G06T 1/60: Memory management
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.

## Claims

### Claim 1

A method comprising:
storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM), the NVRAM being directly accessible by a graphics processor using at least memory store and load commands;
a graphics processor executing a graphics application, wherein the graphics processor at least sends a request using a memory load command for an address corresponding to at least one of the one or more static or near-static graphics resources stored in the NVRAM;
in response to the memory load command, directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
storing a graphics processor memory management unit address map in a volatile memory location accessible to a graphics memory manager logic component;
the graphics memory manager logic component managing a logical address to physical address map for each of a plurality of graphics resources related to the graphics application, wherein the one or more static or near-static graphics resources are part of the plurality of graphics resources related to the graphics application; and
the graphics memory manager logic component including a static/near-static tag for each of the plurality of graphics resources in the graphics processor memory management unit address map, the static/near-static tag indicating the resource will not be dynamically changing in a frequent manner.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
a central processing unit sending the graphics memory manager logic component an update to the static/near-static tag for at least a first graphics resource of the plurality of graphics resources; and
in response to receiving the update to the static/near-static tag for at least the first graphics resource, the graphics memory manager logic component initiating a physical movement of the graphics resource between the NVRAM and the volatile memory.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
storing translation lookaside buffer entries in the graphics processor memory management unit address map.

### Claim 5 (depends on 1)

The method of claim 1, wherein the NVRAM comprises Phase Change Memory and Switch (PCMS).

### Claim 6

A method comprising:
executing a graphics application on a graphics processor, wherein during execution there are one or more dynamic state records, utilized by the graphics application, stored in a volatile memory and at least one or more static or near-static graphics resources, utilized by the graphics application, stored in a non-volatile random access memory (NVRAM), the NVRAM being directly accessible by a graphics processor using at least memory store and load commands;
receiving a notification to suspend the graphics processor, the NVRAM, and the volatile memory;
in response to the notification to suspend, performing a first memory copy of the one or more dynamic state records from the volatile memory to the NVRAM;
after the one or more dynamic state records have been copied into the NVRAM, suspending the graphics processor, the NVRAM, and the volatile memory into a lower power state;
receiving a notification to resume the graphics processor, the NVRAM, and the volatile memory;
in response to the notification to resume, resuming the graphics processor, the NVRAM, and the volatile memory into an operational state;
performing a second memory copy of the one or more dynamic state records from the NVRAM back into the volatile memory; and
resuming execution of the graphics application.

### Claim 7 (depends on 6)

The method of claim 6, wherein suspending to a lower power state further comprises suspending to a non-powered state.

### Claim 8 (depends on 6)

The method of claim 6, further comprising:
building the one or more dynamic state records during an initial startup of execution of the graphics application; and
thereafter not rebuilding the one or more dynamic state records during any subsequent resumption of execution of the graphics application after a suspension of the graphics processor, the NVRAM, and the volatile memory.

### Claim 9 (depends on 6)

The method of claim 6, wherein the NVRAM comprises Phase Change Memory and Switch (PCMS).

### Claim 10

A method, comprising:
storing display image data in at least one frame buffer in a non-volatile random access memory (NVRAM), the NVRAM being directly accessible by a graphics processor using at least memory store and load commands,
a display controller performing a memory load on the frame buffer to receive the display image data, wherein storing the display image data in the NVRAM occurs at least as frequently as a refresh rate of the display screen; and
the display controller displaying the received display image data on a display screen.

### Claim 11 (depends on 10)

The method of claim 10, wherein the NVRAM comprises Phase Change Memory and Switch (PCMS).

### Claim 12

A device comprising:
a graphics processor memory augmentation logic to store one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM), the NVRAM being directly accessible by a graphics processor using at least memory store and load commands;
a graphics processor to execute a graphics application, wherein the graphics processor at least sends a request using a memory load command for an address corresponding to at least one of the one or more static or near-static graphics resources stored in the NVRAM;
a graphics memory controller in response to the memory load command, to directly load the requested graphics resource from the NVRAM into a cache for the graphics processor.

### Claim 13 (depends on 12)

The device of claim 12, further comprising:
a graphics processor memory augmentation logic to store a graphics processor memory management unit address map in a volatile memory location accessible to a graphics memory manager logic component;
the graphics memory manager logic component to manage a logical address to physical address map for each of a plurality of graphics resources related to the graphics application, wherein the one or more static or near-static graphics resources are part of the plurality of graphics resources related to the graphics application; and
and the graphics memory manager logic component to include a static/near-static tag for each of the plurality of graphics resources in the graphics processor memory management unit address map, the static/near-static tag to indicate the resource will not dynamically change in a frequent manner.

### Claim 14 (depends on 13)

The device of claim 13, further comprising:
the graphics memory manager logic component to receive, from a central processing unit, an update to the static/near-static tag for at least a first graphics resource of the plurality of graphics resources; and
in response to receiving the update to the static/near-static tag for at least the first graphics resource, the graphics memory manager logic component to initiate a physical movement of the graphics resource between the NVRAM and the volatile memory.

### Claim 15 (depends on 13)

The device of claim 13, further comprising:
the graphics memory manager logic component to store translation lookaside buffer entries in the graphics processor memory management unit address map.

### Claim 16 (depends on 12)

The method of claim 12, wherein the NVRAM comprises Phase Change Memory and Switch (PCMS).

### Claim 17

A device comprising:
a graphics processor to execute a graphics application, wherein during execution there are one or more dynamic state records, utilized by the graphics application, stored in a volatile memory and at least one or more static or near-static graphics resources, utilized by the graphics application, stored in a non-volatile random access memory (NVRAM), the NVRAM being directly accessible by a graphics processor using at least memory store and load commands;
a graphics processor memory augmentation logic to
receive a notification to suspend the graphics processor, the NVRAM, and the volatile memory;
in response to the notification to suspend, perform a first memory copy of the one or more dynamic state records from the volatile memory to the NVRAM;
after the one or more dynamic state records have been copied into the NVRAM, suspend the graphics processor, the NVRAM, and the volatile memory into a low power state;
receive a notification to resume the graphics processor, the NVRAM, and the volatile memory;
in response to the notification to resume, resume the graphics processor, the NVRAM, and the volatile memory into an operational state;
direct the graphics memory controller to perform a second memory copy of the one or more dynamic state records from the NVRAM back into the volatile memory; and
the graphics processor to resume execution of the graphics application.

### Claim 18 (depends on 17)

The device of claim 17, wherein to suspend to a low power state further comprises to suspend to a non-powered state.

### Claim 19 (depends on 17)

The device of claim 17, further comprising:
the graphics processor to build the one or more dynamic state records during an initial startup of execution of the graphics application; and
thereafter the graphics processor to not rebuild the one or more dynamic state records during any subsequent resumption of execution of the graphics application after a suspension of the graphics processor, the NVRAM, and the volatile memory.

### Claim 20 (depends on 17)

The device of claim 17, wherein the NVRAM comprises Phase Change Memory and Switch (PCMS).

### Claim 21

A system, comprising:
a graphics processor memory augmentation logic to store display image data in at least one frame buffer in a non-volatile random access memory (NVRAM), the NVRAM being directly accessible by a graphics processor using at least memory store and load commands,
a display controller to perform a memory load on the frame buffer to receive the display image data, wherein storing the display image data in the NVRAM occurs at least as frequently as a refresh rate of the display screen; and
the display controller to display the received display image data on a display screen.

### Claim 22 (depends on 21)

The system of claim 21, wherein the NVRAM comprises Phase Change Memory and Switch (PCMS).

### Claim 23 (depends on 21)

The system of claim 21, wherein the display controller includes a local display NVRAM to store one or more frame buffers locally within the display controller.

### Claim 24 (depends on 23)

The system of claim 23, wherein during a current system boot, when the display controller is first capable of sending an image to the display screen, the display controller to display an image that was last stored within the local display NVRAM during an operational period of time prior to the current system boot.