# US 2014/0198114 A1 · Low power display device with variable refresh rates > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0198114 A1 - Document ID: US20140198114A1 - Status: Published application - Kind: A1 - Application number: 14/155,292 - Filed: 2014-01-14 - Published: 2014-07-17 - Earliest claimed: 2013-01-14 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Prasanna Nambi; Jason N. Gomez; Fenghua Zheng; Paolo Sacchetto; Sandro H. Pintz; Taesung Kim; Christopher P. Tann; Marc Albrecht; David W. Lum - Web page: https://patentgrep.com/patent/US20140198114A1 ## CPC - G09G 3/3618: {with automatic refresh of the display panel using sense/write circuits} - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G09G 3/36: using liquid crystals - G09G 3/3611: {Control of matrices with row and column drivers} - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G09G 3/3696: {Generation of voltages supplied to electrode drivers} - G06T 2210/52: Parallel processing - G09G 3/3655: {Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors} - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0626: for control of overall brightness - G09G 2330/02: Details of power systems and of start or stop of display operation - G09G 2330/021: Power management, e.g. power saving - G09G 2340/0435: Change or adaptation of the frame rate of the video stream - G09G 2360/18: Use of a frame buffer in a display terminal, inclusive of the display panel - G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below. ## Claims ### Claim 1 A method for employing a variable refresh rate at a liquid crystal display (LCD), the method comprising: at a display controller, receiving an image control data from a graphics processor unit (GPU) of a host system; at the display controller, evaluating the received image control data to determine a reduced refresh rate (RRR) for a display panel of the LCD; and at the display controller, transmitting display control signaling information associated with the RRR to one or more components of the LCD to affect a transition to the RRR. ### Claim 2 (depends on 1) The method of claim 1, wherein the display control signaling information is further configured to affect one or more image compensation procedures to correct for an image presentation deficiency caused by operating the display panel at the RRR. ### Claim 3 (depends on 2) The method of claim 2, wherein the image presentation deficiency is associated with a decreased luminosity of the display panel or one or more unwanted image artifacts caused by a transition to the RRR. ### Claim 4 (depends on 1) The method of claim 1, wherein the transition to the RRR is a transition from a live refresh rate (LRR) of 50 hertz or above to a RRR of 40 hertz or below. ### Claim 5 (depends on 4) The method of claim 4, wherein the display controller is further configured to affect an immediate exit from the RRR at the display panel by transitioning the display panel from the RRR back to the LRR. ### Claim 6 (depends on 1) The method of claim 1, wherein the display controller is a timing controller comprising clock circuitry that is configured to drive the display panel at one or more RRRs, as designated by the GPU of the host system. ### Claim 7 (depends on 6) The method of claim 6, wherein the timing controller further comprises display buffer drive circuitry for driving a buffer circuit of the LCD, and display panel drive circuitry for controlling a display driver of the display panel. ### Claim 8 (depends on 7) The method of claim 7, wherein the display panel is a thin film transistor (TFT) panel of the LCD and the GPU of the host system includes multiple graphics processors configured to render image frame data to the buffer circuit of the LCD in parallel. ### Claim 9 A timing controller of a liquid crystal display (LCD), comprising: clock circuitry for regulating refresh rate timing; buffer drive circuitry for driving a buffer circuit of the LCD; and display panel drive circuitry for controlling a display driver of a display panel of the LCD, wherein the timing controller is configured to: receive an image control data from a graphics processor unit (GPU) of a host system; evaluate the received image control data to determine a reduced refresh rate (RRR) for the display panel; and transmit display control signaling information associated with the RRR to one or more components of the LCD to affect a transition to the RRR. ### Claim 10 (depends on 9) The timing controller of claim 9, wherein the transition to the RRR is a transition from a live refresh rate (LRR) of 50 hertz or above to a RRR of 40 hertz or below. ### Claim 11 (depends on 9) The timing controller of claim 9, wherein the timing controller is further configured to affect an immediate exit from the RRR at the display panel by transitioning the display panel from the RRR back to the LRR. ### Claim 12 (depends on 9) The timing controller of claim 9, wherein the display control signaling information is further configured to affect one or more image compensation procedures to correct for an image presentation deficiency caused by operating the display panel at the RRR. ### Claim 13 (depends on 12) The timing controller of claim 12, wherein the image presentation deficiency is associated with a decreased luminosity of the display panel or one or more unwanted image artifacts caused by a transition to the RRR. ### Claim 14 (depends on 9) The timing controller of claim 9, wherein the clock circuitry is further configured to drive the display panel at one or more RRRs, as designated by the GPU of the host system. ### Claim 15 (depends on 9) The timing controller of claim 9, wherein the display panel is a thin film transistor (TFT) panel of the LCD and the GPU of the host system includes multiple graphics processors configured to render image frame data to the buffer circuit of the LCD in parallel. ### Claim 16 A method for controlling a refresh rate at a liquid crystal display (LCD), the method comprising: at a timing controller, receiving image control information; at the timing controller, evaluating the received image control information to determine a reduced refresh rate (RRR) for a display panel of the LCD and one or more image presentation deficiencies caused by operation the display panel at the RRR; at the timing controller, transmitting display control signaling information associated with the RRR to one or more components of the LCD to affect a transition to the RRR and to compensate for the one or more image presentation deficiencies. ### Claim 17 (depends on 16) The method of claim 16, wherein the one or more image presentation deficiencies are associated with a decreased luminosity of the display panel or one or more unwanted image artifacts caused by a transition to the RRR. ### Claim 18 (depends on 16) The method of claim 16, wherein: the transition to the RRR is a transition from a live refresh rate (LRR) of 50 hertz or above to a RRR of 40 hertz or below; and the timing controller is further configured to affect an immediate exit from the RRR at the display panel by transitioning the display panel from the RRR back to the LRR. ### Claim 19 (depends on 16) The method of claim 16, wherein the timing controller comprises clock circuitry that is configured to drive the display panel at one or more RRRs, as designated by a GPU of a host system. ### Claim 20 (depends on 16) The method of claim 16, wherein the timing controller further comprises display buffer drive circuitry for driving a buffer circuit of the LCD, and display panel drive circuitry for controlling a display driver of the display panel.