# US 2014/0198083 A1 · Driving circuit and method for driving a display > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0198083 A1 - Document ID: US20140198083A1 - Status: Published application - Kind: A1 - Application number: 14/218,418 - Filed: 2014-03-18 - Published: 2014-07-17 - Earliest claimed: 2010-10-07 - Assignees: Au Optronics Corporation - Applicants: AU Optronics Corporation - Inventors: Yung-Shu Lin; Chun-Fan Chung; Yu-Hsi Ho - Web page: https://patentgrep.com/patent/US20140198083A1 ## CPC - G09G 3/3688: {suitable for active matrices only} - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3614: {Control of polarity reversal in general} - G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters - G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns - G09G 2370/08: Details of image data interface between the display device controller and the data line driver circuit - G09G 2370/14: Use of low voltage differential signaling [LVDS] for display data communication - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract In one aspect of the invention, a driving circuit for driving a display having pixels spatially arranged in a matrix form, includes an input interface for processing input image signals into pixel signals associated with the pixel matrix and grayscales of the display; a timing controller for generating a polarity control signal; a pair of multiplexors electrically coupled to the input interface for receiving the pixel signals therefrom and controlled by the polarity control signal for selecting transmitting paths of the parallel pixel signals; a data register electrically coupled to the pair of multiplexors for stored the pixel signals including its transmitting paths determined by the polarity control signal; and a source driver having a latch array electrically coupled to the data register for receiving the stored pixel signals therefrom, the source driver configured to write the stored pixel signals into the pixel matrix according to the polarity control signal. ## Claims ### Claim 1 A driving circuit for driving a display having a plurality of pixels spatially arranged in a matrix form, comprising: (a) an input interface for processing input image signals into pixel signals associated with the pixel matrix and grayscales of the display; (b) a timing controller for generating a polarity control signal POL; (c) a pair of multiplexors, MUX, electrically coupled to the input interface for receiving the pixel signals therefrom and controlled by the polarity control signal POL for selecting transmitting paths of the parallel pixel signals; (d) a data register electrically coupled to the pair of multiplexors MUX for stored the pixel signals including its transmitting paths determined by the polarity control signal POL; and (e) a source driver having a latch array electrically coupled to the data register for receiving the stored pixel signals therefrom, the source driver configured to write the stored pixel signals into the pixel matrix according to the polarity control signal POL. ### Claim 2 (depends on 1) The driving circuit of claim 1, wherein the data register comprises a series to parallel converter. ### Claim 3 (depends on 1) The driving circuit of claim 1, wherein the polarity control signal POL has a low state, POL(−), and a high state, POL(+), and is alternately in the low and high states POL(−) and POL(+). ### Claim 4 (depends on 1) The driving circuit of claim 1, wherein the input interface comprises a pair of Mini-LVDS input interfaces. ### Claim 5 (depends on 1) The driving circuit of claim 1, wherein the source driver further comprises a shift register electrically coupled to the first latch array. ### Claim 6 A driving circuit for driving a display having a plurality of pixels spatially arranged in a matrix form, comprising: (a) an input interface for processing input image signals into pixel signals associated with the pixel matrix and grayscales of the display; (b) a timing controller for generating a polarity control signal POL; and (c) a source driver comprising: a shift register for generating a plurality of sequential pulses; a pair of multiplexors, MUX, for changing the sequence of the plurality of sequential pulses so as to determine transmitting paths of the pixel signals according to the polarity control signal POL; and a first latch array for latching the pixel signals and its transmitting paths to the pixel matrix according to the polarity control signal POL. ### Claim 7 (depends on 6) The driving circuit of claim 6, further comprising a series to parallel converter for converting a series format of the pixel signals received from the input interface into a parallel format and outputting the parallel pixel signals to the first latch array. ### Claim 8 (depends on 6) The driving circuit of claim 6, wherein the polarity control signal POL has a low state, POL(−), and a high state, POL(+), and is alternately in the low and high states POL(−) and POL(+). ### Claim 9 (depends on 6) The driving circuit of claim 6, wherein the input interface comprises a Mini-LVDS input interface.