# US 2014/0198013 A1 · Backside redistribution layer patch antenna > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0198013 A1 - Document ID: US20140198013A1 - Status: Published application - Kind: A1 - Application number: 13/740,428 - Filed: 2013-01-14 - Published: 2014-07-17 - Earliest claimed: 2013-01-14 - Assignees: Intel Corporation - Inventors: Ruchir Saraswat; Nicholas P. Cowley; Uwe Zillmann - Web page: https://patentgrep.com/patent/US20140198013A1 ## CPC - H10W 70/095: {of vias therein} - H01Q 1/2283: {mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 20/423: {Shielding layers} - H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers} - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H01Q 21/065: {Patch antenna array} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72) ## Abstract A patch antenna system comprising: an integrated circuit die having an active side including an active layer, and a backside; a dielectric layer formed on the backside; and a redistribution layer formed on the dielectric layer wherein the redistribution layer forms an array of patches. The patch antenna further comprises a plurality of through-silicon vias (TSV), wherein the TSVs electrically connect the array of patches to the active layer. ## Claims ### Claim 1 An on-chip antenna comprising: an integrated circuit chip having an active side and a backside; a ground plane; a dielectric formed on said ground plane; and a redistribution layer formed on said dielectric layer, said distribution layer including a one or more patch antenna elements. ### Claim 2 (depends on 1) An on-chip antenna as in claim 1 wherein said backside includes a backside substrate and said ground plane comprises said backside substrate. ### Claim 3 (depends on 2) An on-chip antenna as in claim 2 wherein said dielectric comprises a silicon dioxide layer formed on said backside substrate. ### Claim 4 (depends on 1) An on-chip antenna as in claim 1 wherein said backside includes a backside substrate and said dielectric comprises said backside substrate. ### Claim 5 (depends on 1) An on-chip antenna as in claim 1 wherein said active side includes a metal layer and said ground plane comprises said active side metal layer. ### Claim 6 (depends on 1) An on-chip antenna as in claim 1 wherein said one or more patch antenna elements comprise a phased array. ### Claim 7 A patch antenna system comprising: an integrated circuit die having an active side and a backside; a ground plane; a dielectric formed on said ground plane; a redistribution layer formed on said dielectric layer, said distribution layer including an one or more patch antenna elements; and wherein said active side comprises a transceiver and baseband signal processing circuit. ### Claim 8 (depends on 7) A patch antenna system as in claim 7 wherein said integrated circuit die is mounted on a flip chip package in a flip chip configuration. ### Claim 9 (depends on 8) A patch antenna system as in claim 8 and further including through silicon via structures connecting said patch antenna elements and said transceiver and baseband signal processing circuits. ### Claim 10 (depends on 9) A patch antenna system as in claim 9 wherein: there are a plurality of said patch antenna elements and a plurality of said transceiver and baseband signal processing circuits; one of said transceiver and baseband signal processing circuits is electrically connected to each of said plurality of patch antenna elements by at least one of said through silicon via structures; and said patch antenna system comprises a phased array. ### Claim 11 (depends on 8) A patch antenna system as in claim 8 wherein said backside includes a backside substrate and said ground plane comprises said backside substrate. ### Claim 12 (depends on 8) A patch antenna system as in claim 8 wherein said backside includes a backside substrate and said dielectric comprises said backside substrate. ### Claim 13 (depends on 8) A patch antenna system as in claim 8 wherein there are a plurality of said redistribution layers, said one or more patch elements are formed by a first one of said redistribution layers, and said ground plane is formed by a second one of said redistribution layers. ### Claim 14 (depends on 8) A patch antenna system as in claim 8 wherein the operating frequency of said system is from 58 GHz to 62 GHz. ### Claim 15 (depends on 8) A patch antenna of system as in claim 8, wherein the operating frequency of said system is from 57 GHz and 64 GHz, the length of each of the patches is from 0.45 mm to 1.24 mm, and the width is from 0.98 mm to 1.58 mm. ### Claim 16 An integrated circuit comprising: an integrated circuit die having an active side and a backside; a ground plane; a dielectric formed on said ground plane; and a redistribution layer formed on said dielectric layer, said redistribution layer being formed on said backside of said integrated circuit die and including one or more patch antenna elements. ### Claim 17 (depends on 16) An integrated circuit as in claim 16 wherein said backside includes a backside substrate and said ground plane comprises said backside substrate. ### Claim 18 (depends on 16) An integrated circuit as in claim 16 wherein said backside includes a backside substrate and said dielectric comprises said backside substrate. ### Claim 19 A method of fabricating a patch antenna, said method comprising: providing an integrated circuit die comprising an active side including an active layer and a backside; forming a dielectric layer on said backside; and forming a redistribution layer on said dielectric layer said distribution layer including a one or more patch antenna elements. ### Claim 20 (depends on 19) The method of fabricating a patch antenna as in claim 19 and further comprising forming one or more through-silicon vias (TSVs) electrically connecting the said one or more patch antenna elements to said active layer.