# US 2014/0197971 A1 · Systems and methods for providing a pipelined analog-to-digital converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197971 A1 - Document ID: US20140197971A1 - Status: Published application - Kind: A1 - Application number: 14/005,887 - Filed: 2012-03-19 - Published: 2014-07-17 - Earliest claimed: 2011-03-18 - Assignees: The Trustees of Columbia University in the City of New York - Inventors: Jayanth Kuppambatti; Junhua Shen; Peter Kinget - Web page: https://patentgrep.com/patent/US20140197971A1 ## CPC - H03M 1/002: {Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed} - G06F 1/08: Clock generators with changeable or programmable clock frequency - H03M 1/1245: {Details of sampling arrangements or methods} - H03M 1/442: {using switched capacitors} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage. ## Claims ### Claim 1 A system for providing a pipelined Analog-to-Digital Converter, comprising: a first multiplying Digital-to-Analog Converter (MDAC) stage comprising: a sub-Analog-to-Digital Converter (ADC) that outputs a value based on an input signal; at least two reference capacitors that are charged to a reference voltage; at least two sampling capacitors that are charged to a sampling voltage: and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage. ### Claim 2 (depends on 1) The system of claim 1, wherein the first MDAC stage further comprises a first current source coupled to a first of the at least two reference capacitors and a second current source coupled to a second of the at least two reference capacitors, ### Claim 3 (depends on 2) The system of claim 2, wherein the first current source and the second current source are cascoded current sources. ### Claim 4 (depends on 2) The system of claim 2, wherein the first current source charges the first of the at least two reference capacitors for a given period of time and the second current source charges the second of the at least two reference capacitors for the given period of time. ### Claim 5 (depends on 1) The system of claim 1, wherein the first MDAC stage further comprises a zero-crossing detector that controls how long the at least two sampling capacitors are coupled to an input voltage. ### Claim 6 (depends on 5) The system of claim 5, wherein the first MDAC stage further comprises a delay circuit that receives an output signal of the zero-crossing detector and provides a delayed signal that controls when the at least two sampling capacitors are coupled to the input voltage. ### Claim 7 (depends on 1) The system of claim 1, wherein the sub-ADC is as comparator. ### Claim 8 (depends on 1) The system of claim 1, wherein the sub-ADC is a flash ADC. ### Claim 9 (depends on 1) The system of claim 1, wherein the first MDAC stage is a differential MDAC stage. ### Claim 10 (depends on 1) The system of claim 1, wherein the at least two reference capacitors are half the size of the at least two sampling capacitors. ### Claim 11 A method for providing a pipelined Analog-to-Digital Converter, comprising: in a first multiplying Digital-to-Analog Converter (MDAC) stage: outputting from a sub-Analog-to-Digital Converter (ADC) a value based on an input signal; charging at least two reference capacitors to a reference voltage; charging at least two sampling capacitors to a sampling voltage, and using a plurality of switches to couple the at least two reference capacitors so that they are charged during a sampling, phase, to couple the at least two sampling capacitors so that they are charged during the sampling phase, to couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and to couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage. ### Claim 12 (depends on 11) The method of claim 11, charging a first of the at least two reference capacitors using, a first current source and charging a second of the at least two reference capacitors using a second current source. ### Claim 13 (depends on 12) The method of claim 12, wherein the first current source and the second current source are cascoded current sources, ### Claim 14 (depends on 12) The method of claim 12, wherein the first current source charges the first of the at least two reference capacitors for a given period, of time and the second current source charges the second of the at least two reference capacitors for the given period of time. ### Claim 15 (depends on 11) The method of claim 11, wherein controlling how long the at least two sampling capacitors are coupled to an input voltage using a zero-crossing detector. ### Claim 16 (depends on 15) The method of claim 15, further comprising providing a delayed signal that controls when the at least two sampling capacitors are coupled to the input voltage in response to an output of the zero-crossing detector. ### Claim 17 (depends on 11) The method of claim 11, wherein the sub-ADC is a comparator. ### Claim 18 (depends on 11) The method of claim 11, wherein the sub-ADC is a flash ADC. ### Claim 19 (depends on 11) The method of claim 11, wherein the first MDAC stage is a differential MDAC stage. ### Claim 20 (depends on 11) The method of claim 11, wherein the at least two reference capacitors are half the size of the at least two sampling capacitors.