# US 2014/0197895 A1 · Variability and aging sensor for integrated circuits

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- Number: US 2014/0197895 A1
- Document ID: US20140197895A1
- Status: Published application
- Kind: A1
- Application number: 14/157,009
- Filed: 2014-01-16
- Published: 2014-07-17
- Earliest claimed: 2013-01-17
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: MIN CHEN; VIJAY KUMAR REDDY
- Web page: https://patentgrep.com/patent/US20140197895A1

## CPC

- H03K 3/0315: {Ring oscillators}
- G01R 31/2882: {Testing timing characteristics}
- G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack. A feedback connection is from an output of the last stage to an input of the first stage. At least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device is coupled between the first gate stack and a ground pad, and/or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device is coupled between the second gate stack a power supply pad.

## Claims

### Claim 1

A ring-oscillator-based on-chip sensor (OCS), comprising:
a substrate having a semiconductor surface upon which said OCS is formed; said OCS including:
an odd number of digital logic stages formed in and on said semiconductor surface including:
a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack;
a feedback connection from an output of said last stage to an input of said first stage, and
at least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device coupled between said first gate stack and a ground pad, or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device coupled between said second gate stack a power supply pad.

### Claim 2 (depends on 1)

The OCS of claim 1, wherein said OCS includes said NOR gate, provides said discharge path, and further includes at least a second PMOS device having an enable input in series with said first PMOS device.

### Claim 3 (depends on 1)

The OCS of claim 1, wherein said OCS includes said NAND gate, provides said charge path, and further includes at least a second NMOS device having an enable input in series with said first NMOS device.

### Claim 4 (depends on 3)

The OCS of claim 3, wherein said OCS further includes said NOR gate, provides said discharge path, and further includes at least a second PMOS device having an enable input in series with said first PMOS device.

### Claim 5 (depends on 1)

The OCS of claim 1, wherein said OCS is formed on said semiconductor surface.

### Claim 6 (depends on 1)

The OCS of claim 1, wherein said at least one discharge path includes a plurality of said discharge paths electrically in parallel, and/or wherein said at least one charge path includes a plurality of said charge paths electrically in parallel.

### Claim 7 (depends on 4)

The OCS of claim 4, further comprising a system on a chip (SOC) sharing said semiconductor surface with said OCS, said SOC providing a scan controlled digital bank that controls enable inputs which are coupled to at least one of said enable input of said second PMOS device and said enable input of said second NMOS device.

### Claim 8

A system on a chip (SOC), comprising:
a substrate having a semiconductor surface upon which said SOC is formed; said SOC including:
digital circuitry, analog circuitry, and mixed-signal circuitry in and on said semiconductor surface; and
a ring-oscillator-based on-chip sensor (OCS) in and on said semiconductor surface; including:
an odd number of digital logic stages formed in and on said semiconductor surface including:
a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack;
a feedback connection from an output of said last stage to an input of said first stage, and
at least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device coupled between said first gate stack and a ground pad, or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device coupled between said second gate stack a power supply pad.

### Claim 9 (depends on 8)

The SOC of claim 8, wherein said OCS includes said NOR gate, provides said discharge path, and further includes at least a second PMOS device having an enable input in series with said first PMOS device.

### Claim 10 (depends on 8)

The SOC of claim 8, wherein said OCS includes said NAND gate, provides said charge path, and further includes at least a second NMOS device having an enable input in series with said first NMOS device.

### Claim 11 (depends on 10)

The SOC of claim 10, wherein said OCS further includes said NOR gate, provides said discharge path, and further includes at least a second PMOS device having an enable input in series with said first PMOS device.

### Claim 12 (depends on 8)

The SOC of claim 8, wherein said at least one discharge path includes a plurality of said discharge paths electrically in parallel, and/or wherein said at least one charge path includes a plurality of said charge paths electrically in parallel.

### Claim 13 (depends on 11)

The SOC of claim 11, wherein said SOC provides a scan controlled digital bank that controls enable inputs which are coupled to at least one of said enable input of said second PMOS device and said enable input of said second NMOS device.

### Claim 14 (depends on 11)

The SOC of claim 11, wherein said OCS, said digital circuitry, said analog circuitry, and said mixed-signal circuitry all include MOS devices having a gate stack comprising a metal gate on a high-k dielectric.

### Claim 15

A method for adaptively scaling voltage in an integrated circuit (IC), the method comprising:
providing a ring-oscillator-based on-chip sensor (OCS), including a substrate having a semiconductor surface upon which said OCS is formed; said OCS including an odd number of digital logic stages formed in and on said semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack; a feedback connection from an output of said last stage to an input of said first stage, and at least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device coupled between said first gate stack and a ground pad, or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device coupled between said second gate stack a power supply pad,
obtaining a frequency measurement from said OCS;
determining a change in at least one voltage selected from VDD, Vbn and Vbp for said IC from said frequency measurement.

### Claim 16 (depends on 15)

The method of claim 15, wherein said OCS further includes said NOR gate, provides said discharge path, and further includes at least a second PMOS device having an enable input in series with said first PMOS device or a second NMOS device having an enable input in series with said first NMOS device, said method further comprising:
using a scan controlled digital bank to control enable inputs which are coupled to at least one of said enable input of said second PMOS device and said enable input of said second NMOS device.

### Claim 17 (depends on 15)

The method of claim 15, further comprising scanning gates of said OCS having said enable inputs with a scan code, wherein a strength of said discharge path and/or said charge path is varied through said scan code such that a VDD of said OCS (OCS VDD) is higher than a logic VDD on product circuitry to be guardbanded by said OCS so as to provide a bounding guardband.