# US 2014/0197886 A1 · Amplifier with switchable common gate gain buffer

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- Number: US 2014/0197886 A1
- Document ID: US20140197886A1
- Status: Published application
- Kind: A1
- Application number: 13/899,091
- Filed: 2013-05-21
- Published: 2014-07-17
- Earliest claimed: 2013-01-17
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Rajagopalan Rangarajan; Chirag D. Patel
- Web page: https://patentgrep.com/patent/US20140197886A1

## CPC

- H03F 3/2171: {with field-effect devices (H03F3/2173 - H03F3/2178 take precedence)}
- H03F 3/72: Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03G 1/0029: {using field-effect transistors [FET]}
- H03G 1/0088: {using discontinuously variable devices, e.g. switch-operated}
- H03G 3/3052: {in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver (H03G3/32, H03G3/34 take precedence)}
- H03F: AMPLIFIERS
- H03G: CONTROL OF AMPLIFICATION

## Abstract

An amplifier having a switchable common gate gain buffer is disclosed. In an exemplary embodiment, an apparatus includes a plurality of selectable gain channels that provide constant input impedance at a common input to receive an input signal and generate an output signal having at least one of selected gain and current characteristics. At least two gain channels utilize transistors having different transconductance values. The apparatus also includes at least one impedance network coupled to at least one gain channel to provide the constant input impedance.

## Claims

### Claim 1

An apparatus comprising:
a plurality of selectable gain channels that provide constant input impedance at a common input to receive an input signal and generate an output signal having at least one of selected gain and current characteristics, and wherein at least two gain channels utilize transistors having different transconductance values; and
at least one impedance network coupled to at least one gain channel to provide the constant input impedance.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising at least one control signal configured to select at least one of the gain channels to generate the output signal.

### Claim 3 (depends on 1)

The apparatus of claim 1, the at least one impedance network comprises at least one of a resistor, a capacitor, and an inductor.

### Claim 4 (depends on 1)

The apparatus of claim 1, each gain channel comprising at least one cascode transistor pair that is enabled by switchable bias voltages.

### Claim 5 (depends on 1)

The apparatus of claim 1, the input impedance is configured for 50 ohms.

### Claim 6 (depends on 1)

The apparatus of claim 1, the selected gain of the output signal is determined by a gain associated with the input signal and a gain associated with a selected gain channel.

### Claim 7 (depends on 1)

The apparatus of claim 1, the apparatus is configured as a common gate buffer.

### Claim 8 (depends on 1)

The apparatus of claim 1, further comprising an amplifier that generates the input signal.

### Claim 9 (depends on 1)

The apparatus of claim 1, at least one gain channel configured to consume less current while providing the same or lower gain as other gain channels.

### Claim 10

An apparatus comprising:
means for providing a plurality of selectable gain channels that provide constant input impedance at a common input to receive an input signal and generate an output signal having at least one of selected gain and current characteristics, and wherein at least two gain channels utilize transistors having different transconductance values; and
means for providing at least one impedance network coupled to at least one gain channel to provide the constant input impedance.

### Claim 11 (depends on 10)

The apparatus of claim 10, further comprising means for providing at least one control signal configured to select at least one of the gain channels to generate the output signal.

### Claim 12 (depends on 10)

The apparatus of claim 10, the means for providing the at least one impedance network comprising at least one of a resistor, a capacitor, and an inductor.

### Claim 13 (depends on 10)

The apparatus of claim 10, each gain channel comprising at least one cascode transistor pair that is enabled by switchable bias voltages.

### Claim 14 (depends on 10)

The apparatus of claim 10, the input impedance is configured for 50 ohms.

### Claim 15 (depends on 10)

The apparatus of claim 10, the selected gain of the output signal is determined by a gain associated with the input signal and a gain associated with a selected gain channel.

### Claim 16 (depends on 10)

The apparatus of claim 10, the apparatus is configured as a common gate buffer.

### Claim 17 (depends on 10)

The apparatus of claim 10, further comprising means for amplification to generate the input signal.

### Claim 18 (depends on 10)

The apparatus of claim 10, at least one gain channel configured to consume less current while providing the same or lower gain as other gain channels.