# US 2014/0197884 A1 · On-chip port current control arrangement > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197884 A1 - Document ID: US20140197884A1 - Status: Published application - Kind: A1 - Application number: 14/143,025 - Filed: 2013-12-30 - Published: 2014-07-17 - Earliest claimed: 2013-01-17 - Assignees: Microsemi Corp.—Analog Mixed Signal Group Ltd. - Applicants: Microsemi Corp. - Analog Mixed Signal Group, Ltd. - Inventors: Shimon COHEN - Web page: https://patentgrep.com/patent/US20140197884A1 ## CPC - H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators - G05F 1/561: {Voltage to current converters (amplifiers H03F)} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract A port current control arrangement, constituted of: a current source arranged to generate a reference current or a predetermined value; an on-chip reference resistor, the generated reference current arranged to produce a reference voltage across the on-chip reference resistor; an on-chip sense resistor, a port current arranged to flow through the on-chip sense resistor and produce a sense voltage across the on-chip sense resistor, wherein the resistance of the on-chip sense resistor exhibits a predetermined relationship with the resistance of the first on-chip reference resistor; and a current control circuit, a first input of the current control circuit arranged to receive the produced reference voltage and a second input of the current control circuit arranged to receive the sense voltage, wherein the current control circuit is arranged to limit the port current to a value responsive to the received reference voltage and the received sense voltage. ## Claims ### Claim 1 A port current control arrangement, comprising: a current source arranged to generate a reference current of at least one predetermined value; an on-chip reference resistor, an end of said on-chip reference resistor coupled to said current source, said generated reference current arranged to produce a reference voltage across said on-chip reference resistor; an on-chip sense resistor, a port current arranged to flow through said on-chip sense resistor and produce a sense voltage across said on-chip sense resistor, wherein the resistance of said on-chip sense resistor exhibits a predetermined relationship with the resistance of said on-chip reference resistor; and a current control circuit, a first input of said current control circuit arranged to receive said produced reference voltage and a second input of said current control circuit arranged to receive said sense voltage, wherein said current control circuit is arranged to limit the port current to a value responsive to the received reference voltage and the received sense voltage. ### Claim 2 (depends on 1) The port current control arrangement of claim 1, wherein said current control circuit comprises: a differential amplifier, a first input of said differential amplifier arranged to receive said reference voltage and a second input of said differential amplifier arranged to receive said sense voltage; and an electronically controlled switch, a first terminal of said electronically controlled switch coupled to said sense resistor, a second terminal of said electronically controlled switch arranged to receive the port current and a control terminal of said electronically switch coupled to an output of said differential amplifier, wherein said limit of the port current is responsive to the operation of said differential amplifier in cooperation with said electronically controlled switch. ### Claim 3 (depends on 2) The port current control arrangement of claim 2, wherein said differential amplifier is arranged to adjust the resistance between the first terminal and second terminal of said electronically controlled switch responsive to the difference between said received reference voltage and said received sense voltage, said limit of the port current responsive to said resistance adjustment. ### Claim 4 (depends on 1) The port current control arrangement of claim 1, further comprising a current measuring circuitry, a first input of said current measuring circuitry arranged to receive said reference voltage and a second input of said current measuring circuitry arranged to receive said sense voltage, wherein said current measuring circuitry is arranged to determine the port current responsive to said received reference voltage and said received sense voltage. ### Claim 5 (depends on 4) The on-chip current arrangement of claim 4, wherein said current measuring circuitry comprises: a multiplexer, a first input of said multiplexer arranged to receive said reference voltage and a second input of said multiplexer arranged to receive said sense voltage; a current measuring circuitry control, an input of said current measuring circuitry control coupled to an output of said multiplexer and an output of said current measuring circuitry control coupled to a control port of said multiplexer, wherein said current measuring circuitry control is arranged to: control said multiplexer to alternately output a signal responsive to said received reference voltage and a signal responsive to said received sense voltage; determine the port current responsive to said alternately output signals; and output data regarding the determined port current. ### Claim 6 (depends on 4) The on-chip current arrangement of claim 4, wherein the current source is arranged to generate a plurality of predetermined values responsive to the current measuring circuitry. ### Claim 7 (depends on 4) The on-chip current arrangement according to claim 4, wherein said on-chip sense resistor comprises a plurality of on-chip sense resistor and a multiplexer, said multiplexer responsive to an output of said current measuring circuitry to thereby select one of a plurality of reference voltages across said on-chip reference resistor. ### Claim 8 An on-chip port current control arrangement, comprising: a means for generating a reference current; an on-chip reference means for providing electrical resistance, an end of said on-chip reference means for providing electrical resistance coupled to said means for generating the reference current, said generated reference current arranged to produce a reference voltage across said on-chip reference means for providing electrical resistance; an on-chip sense means for providing electrical resistance, a port current arranged to flow through said on-chip sense means for providing electrical resistance and produce a sense voltage across said on-chip sense means for providing electrical resistance; and a means for controlling current, a first input of said means for controlling current arranged to receive said produced reference voltage and a second input of said means for controlling current arranged to receive said sense voltage, wherein the electrical resistance of said on-chip sense means for providing electrical resistance exhibits a predetermined relationship with the resistance of said on-chip reference means for providing electrical resistance, and wherein said means for controlling current is arranged to limit the port current to a value responsive to the received reference voltage and the received sense voltage. ### Claim 9 (depends on 8) The on-chip port current arrangement of claim 8, wherein said means for controlling current comprises: a means for amplifying a voltage difference, a first input of said means for amplifying a voltage difference arranged to receive said reference voltage and a second input of said differential amplifier arranged to receive said sense voltage; and a means for controlling a current path, a first terminal of said means for controlling a current path coupled to said sense means for providing electrical resistance, a second terminal of said means for controlling a current path arranged to receive the port current and a control terminal of said means for controlling a current path coupled to an output of said means for amplifying a voltage difference, wherein said limit of the port current is responsive to the operation of said means for amplifying a voltage difference in cooperation with said means for controlling a current path. ### Claim 10 (depends on 9) The on-chip current arrangement of claim 9, wherein said means for amplifying a voltage difference is arranged to adjust the resistance between the first terminal and second terminal of said means for controlling a current path responsive to the difference between said received reference voltage and said received sense voltage, said limit of the port current responsive to said resistance adjustment. ### Claim 11 (depends on 8) The on-chip current arrangement of claim 8, further comprising a means for measuring current, a first input of said means for measuring current arranged to received said reference voltage and a second input of said means for measuring current arranged to receive said sense voltage, wherein said means for measuring current is arranged to measure the port current responsive to said received reference voltage and said received sense voltage. ### Claim 12 (depends on 11) The on-chip current arrangement of claim 11, wherein said means for measuring current comprises: a means for alternately outputting a signal responsive to a first input and a second input, a first input of said means for alternately outputting coupled to receive said reference voltage and a second input of said means for alternately outputting coupled to receive said sense voltage, wherein said means for measuring current is arranged to: control said means for alternately outputting to alternately output a signal responsive to said received reference voltage and a signal responsive to said received sense voltage; determine the port current responsive to said output signal responsive to said received reference voltage and said output signal responsive to said received sense voltage; and output data regarding the determined port current. ### Claim 13 (depends on 11) The on-chip current arrangement of claim 11, wherein the current source is arranged to generate a plurality of predetermined values responsive to the means for measuring current. ### Claim 14 (depends on 11) The on-chip current arrangement according to claim 11, wherein said on-chip sense resistor comprises a plurality of on-chip sense resistor and a multiplexer, said multiplexer responsive to an output of the means for measuring current to thereby select one of a plurality of reference voltages across said on-chip reference resistor. ### Claim 15 A method of managing a port current, the method comprising: provide an on-chip sense resistor; provide an on-chip reference resistor, wherein the resistance of said provided on-chip sense resistor exhibits a predetermined relationship with the resistance of said provided on-chip reference resistor; generating a reference current; producing a reference voltage across said provided on-chip reference resistor responsive to said generated reference current; receiving the port current; producing a sense voltage across said provided on-chip sense resistor responsive to the port current; and limiting the port current to a value responsive to said produced reference voltage and said produced sense voltage. ### Claim 16 (depends on 15) The method of claim 15, further comprising: amplifying the difference between said produced reference voltage and said produced sense voltage, wherein said limiting the port current is responsive to said amplified difference. ### Claim 17 (depends on 16) The method of claim 16, wherein the port current is arranged to flow through an electronically controlled switch from a first terminal of the electronically controlled switch to a second terminal of the electronically controlled switch, and wherein said limiting the port current is by controlling the resistance between the first terminal and second terminal of the electronically controlled switch responsive to said amplified difference. ### Claim 18 (depends on 15) The method of claim 15, further comprising measuring the port current responsive to said produced reference voltage and said produced sense voltage. ### Claim 19 (depends on 18) The method of claim 18, further comprising providing a multiplexer, wherein a first input of a multiplexer is arranged to receive said produced reference voltage and a second input of the multiplexer is arranged to receive said produced sense voltage, and wherein said measuring of the port current comprises: controlling the provided multiplexer to output a signal alternately responsive to said received reference voltage and to said received sense voltage; and determining the port current responsive to said alternately output signals.