# US 2014/0197879 A1 · Method and apparatus for reducing crowbar current > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197879 A1 - Document ID: US20140197879A1 - Status: Published application - Kind: A1 - Application number: 13/742,925 - Filed: 2013-01-16 - Published: 2014-07-17 - Earliest claimed: 2013-01-16 - Assignees: QUALCOMM Incorporated - Applicants: Qualcomm Incorporated - Inventors: Yu Huang - Web page: https://patentgrep.com/patent/US20140197879A1 ## CPC - H03K 17/165: {by feedback from the output circuit to the control circuit} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Techniques for reducing crowbar current are disclosed. In one embodiment, a circuit for reducing crowbar current comprises an inverter having an input and an output, a first switch coupled between the inverter and a first power supply rail, and a second switch coupled between the inverter and a second power supply rail. The circuit also comprises a feedback circuit coupled to the output of the inverter, wherein the feedback circuit is configured to turn off the first switch when the output of the inverter is in a low output state, and to turn off the second switch when the output of the inverter is in a high output state. ## Claims ### Claim 1 A circuit for reducing crowbar current, comprising: an inverter having an input and an output; a first switch coupled between the inverter and a first power supply rail; a second switch coupled between the inverter and a second power supply rail; and a feedback circuit coupled to the output of the inverter, wherein the feedback circuit is configured to turn off the first switch when the output of the inverter is in a low output state, and to turn off the second switch when the output of the inverter is in a high output state. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the first switch comprises a PMOS transistor having a source coupled to the first power supply rail, and a drain coupled to the inverter. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the feedback circuit comprises a second inverter having an input coupled to the output of the first inverter, and an output coupled to a gate of the PMOS transistor of the first switch. ### Claim 4 (depends on 1) The circuit of claim 1, wherein the second switch comprises an NMOS transistor having a drain coupled to the first inverter, and a source coupled to the second power supply rail. ### Claim 5 (depends on 4) The circuit of claim 4, wherein the feedback circuit comprises a second inverter having an input coupled to the output of the first inverter, and an output coupled to a gate of the NMOS transistor of the second switch. ### Claim 6 (depends on 1) The circuit of claim 1, further comprising a trigger device coupled between the first power supply rail and the inverter, wherein the trigger device is configured to provide a current path between the first power supply rail and the inverter when the input of the inverter transitions from a high input state to a low input state. ### Claim 7 (depends on 6) The circuit of claim 6, wherein the trigger device comprises a diode. ### Claim 8 (depends on 7) The circuit of claim 7, wherein the diode comprises a diode-connected PMOS transistor. ### Claim 9 (depends on 1) The circuit of claim 1, further comprising a trigger device coupled between the inverter and the second power supply rail, wherein trigger device is configured to provide a current path between the inverter and the second power supply rail when the input of the inverter transitions from the low input state to the high input state. ### Claim 10 (depends on 9) The circuit of claim 9, wherein the trigger devices comprises a diode. ### Claim 11 (depends on 10) The circuit of claim 10, wherein the diode comprises a diode-connected NMOS transistor. ### Claim 12 (depends on 1) The circuit of claim 1, wherein the feedback circuit is configured to turn on the first switch when the output of the inverter is in the high output state, and to turn on the second switch when the output of the inverter is in the low output state. ### Claim 13 (depends on 1) The circuit of claim 1, wherein the feedback circuit comprises a second inverter having an input coupled to the output of the first inverter, and an output coupled to the first and second switches. ### Claim 14 (depends on 1) The circuit of claim 1, wherein the inverter comprises: a PMOS transistor having a source coupled to the first switch, a gate coupled to the input of the inverter, and a drain coupled to the output of the inverter; and an NMOS transistor having a source coupled to the second switch, a gate coupled to the input of the inverter, and a drain coupled to the output of the inverter. ### Claim 15 A method for reducing crowbar current in a circuit including an inverter having an input and an output, a first switch coupled between the inverter and a first power supply rail, and a second switch coupled between the inverter and a second power supply rail, the method comprising: turning off the first switch when the output of the inverter is in a low output state; and turning off the second switch when the output of the inverter is in a high output state. ### Claim 16 (depends on 15) The method of claim 15, wherein the first switch comprises a PMOS transistor having a source coupled to the first power supply rail, and a drain coupled to the inverter, and wherein turning off the first switch comprises: inverting the output of the inverter; and inputting the inverted output of the inverter to a gate of the PMOS transistor. ### Claim 17 (depends on 15) The method of claim 15, wherein the second switch comprises an NMOS transistor having a drain coupled to the first inverter, and a source coupled to the second power supply rail, and wherein turning off the second switch comprises: inverting the output of the inverter; and inputting the inverted output of the inverter to a gate of the NMOS transistor. ### Claim 18 (depends on 15) The method of claim 15, further comprising: providing a current path from the first power supply rail to the inverter when the input of the inverter transitions from a high input state to a low input state, wherein the current path bypasses the first switch. ### Claim 19 (depends on 15) The method of claim 15, further comprising: providing a current path from the inverter to the second power supply rail when the input of the inverter transitions from a low input state to a high input state, wherein the current path bypasses the second switch. ### Claim 20 (depends on 15) The method of claim 15, further comprising: turning on the first switch when the output of the inverter is in the high output state; and turning on the second switch when the output of the inverter is in the low output state. ### Claim 21 An apparatus for reducing crowbar current, comprising: means for inverting a signal; first means for switching coupled between the means for inverting and a first power supply rail; second means for switching coupled between the means for inverting and a second power supply rail; means for turning off the first means for switching when an output of the means for inverting is in a low output state; and means for turning off the second means for switching when the output of the means for inverting is in a high output state. ### Claim 22 (depends on 21) The apparatus of claim 21, wherein the first means for switching comprises a PMOS transistor having a source coupled to the first power supply rail, and a drain coupled to the means for inverting. ### Claim 23 (depends on 22) The apparatus of claim 22, wherein the means for turning off the first means for switching comprises: second means for inverting the output of the first means for inverting; and means for inputting the inverted output of the first means for inverting to a gate of the PMOS transistor. ### Claim 24 (depends on 21) The apparatus of claim 21, wherein the second means for switching comprises an NMOS transistor having a drain coupled to the means for inverting, and a source coupled to the second power supply rail. ### Claim 25 (depends on 24) The apparatus of claim 24, wherein the means for turning off the second means for switching comprises: second means for inverting the output of the first means for inverting; and means for inputting the inverted output of the first means for inverting to a gate of the NMOS transistor. ### Claim 26 (depends on 21) The apparatus of claim 21, further comprising: means for providing a current path from the first power supply rail to the means for inverting when the input of the means for inverting transitions from a high input state to a low input state, wherein the current path bypasses the first means for switching. ### Claim 27 (depends on 26) The apparatus of claim 26, wherein the means for providing the current path comprises a diode. ### Claim 28 (depends on 21) The apparatus of claim 21, further comprising: means for providing a current path from the means for inverting to the second power supply rail when the input of the means for inverting transitions from a low input state to a high input state, wherein the current path bypasses the second means for switching. ### Claim 29 (depends on 28) The apparatus of claim 28, wherein the means for providing the current path comprises a diode. ### Claim 30 (depends on 21) The apparatus of claim 21, further comprising: means for turning on the first means for switching when the output of the means for inverting is in the high output state; and means for turning on the second means for switching when the output of the means for inverting is in the low output state.