# US 2014/0197876 A1 · Semiconductor Device with IGBT Cell and Desaturation Channel Structure

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- Number: US 2014/0197876 A1
- Document ID: US20140197876A1
- Status: Published application
- Kind: A1
- Application number: 13/743,918
- Filed: 2013-01-17
- Published: 2014-07-17
- Earliest claimed: 2013-01-17
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Johannes Georg Laven; Hans-Joachim Schulze
- Web page: https://patentgrep.com/patent/US20140197876A1

## CPC

- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H03K 3/012: Modifications of generator to improve response time or to decrease power consumption
- H03K 17/04113: {in bipolar transistor switches (H03K17/0412, H03K17/0416 take precedence)}
- H03K 17/567: Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
- H03K 17/60: the devices being bipolar transistors (bipolar transistors having four or more electrodes H03K17/72)
- H10D 12/01: Manufacture or treatment
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/411: {Insulated-gate bipolar transistors [IGBT]}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/314: {having vertical doping variations (vertical IGFETs H10D30/63)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/01348: {with substrate doping, e.g. N, Ge or C implantation, before formation of the insulator}
- H10D 64/01352: {with sacrificial oxide}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 30/22: using masks
- H10P 32/1406: {by ion implantation}
- H10P 32/171: {being group IV material}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes an IGBT cell including a second-type doped drift zone, and a desaturation semiconductor structure for desaturating a charge carrier concentration in the IGBT cell. The desaturation structure includes a first-type doped region forming a pn-junction with the drift zone, and two portions of a trench or two trenches arranged in the first-type doped region and beside the IGBT cell in a lateral direction. Each of the two trench portions or each of the two trenches has a wide part below a narrow part. The wide parts confine a first-type doped desaturation channel region of the first-type doped region at least in the lateral direction. The narrow parts confine a first-type doped mesa region of the first-type doped region at least in the lateral direction. The desaturation channel region has a width smaller than the mesa region in the lateral direction, and adjoins the mesa region.

## Claims

### Claim 1

A semiconductor device, comprising:
a first IGBT cell comprising a second-type doped drift zone; and
a desaturation semiconductor structure for desaturating a charge carrier concentration in the first IGBT cell, the desaturation semiconductor structure comprising:
a first-type doped region forming a pn-junction with the drift zone,
two portions of a trench or two trenches arranged in the first-type doped region and arranged beside the first IGBT cell in a lateral direction, each of the two trench portions or each of the two trenches having a wide part below a narrow part, the wide parts confining a first-type doped desaturation channel region of the first-type doped region at least in the lateral direction and the narrow parts confining a first-type doped mesa region of the first-type doped region at least in the lateral direction, wherein the desaturation channel region has a width smaller than the mesa region in the lateral direction, and wherein the desaturation channel region and the mesa region adjoin each other.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a first electrode terminal connected to a source region of the IGBT cell;
a gate electrode terminal connected to a gate electrode of the IGBT cell; and
a conductive material in the two trench portions or in the two trenches,
wherein the first-type doped mesa region is connected to the first electrode terminal, and the conductive material in the two trench portions or in the two trenches is connected to the gate electrode terminal.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the desaturation channel region has a threshold voltage for switching-off a conductive path through the desaturation channel region, and the IGBT cell has a threshold voltage for providing an inversion channel, wherein the absolute value of the threshold voltage for switching-off the conductive path through the desaturation channel region is higher than the absolute value of the threshold for providing an inversion channel of the IGBT cell.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein an outer region of the first-type doped region outside of the two trench portions or of the two trenches adjoins the desaturation channel region, and wherein the first-type doping of the desaturation channel region is lower than at least one of the first-type doping of the mesa region and the first-type doping of the outer region.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the first-type doped mesa region constitutes the entire space confined in the lateral direction by the narrow parts of the two trench portions or the two trenches.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a second IGBT cell,
wherein the desaturation semiconductor structure is arranged between the first IGBT cell and the second IGBT cell, the first-type doped region extends at least between the first IGBT cell and the second IGBT cell, and the desaturation semiconductor structure is adapted for desaturating charge carrier concentrations in drift regions of the first and second IGBT cells.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein a conductive semiconductor material in the two trench portions or in the two trenches is separated by an oxide layer and/or by a second-type doped layer from the mesa region, from the desaturation region and from an outer region of the first-type doped region, the outer region being located outside of the two trench portions or of the two trenches and adjoining the desaturation channel region.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein at least one of :
(i) the semiconductor device is a power semiconductor device;
(ii) the first-type doping is a p-type doping;
(iii) the wide parts are at least 20% wider than the narrow parts of the two trench portions or of the two trenches;
(iv) the first-type doping in the desaturation channel region is at least 50% smaller than the first-type doping in the mesa region;
(v) the first-type doping in the desaturation channel region is at least 50% smaller than the first-type doping in an outer region of the first-type doped region, the outer region being located outside of the two trench portions or of the two trenches and adjoining the desaturation channel region; and
(vi) the desaturation channel region is at least 50% narrower than the mesa region.

### Claim 9

A semiconductor device, comprising:
a first IGBT cell comprising a second-type doped drift zone; and
a desaturation semiconductor structure for desaturating a charge carrier concentration in the first IGBT cell, the desaturation semiconductor structure comprising:
a first-type doped region forming a pn-junction with the drift zone,
two portions of a trench or two trenches arranged in the first-type doped region and arranged beside the first IGBT cell in a lateral direction, wherein the two trench portions or the two trenches confine a mesa region comprising a first-type doped desaturation channel region and a first-type doped body region at least in the lateral direction, wherein the first-type doping of the desaturation channel region is lower than the first-type doping of the body region, wherein the desaturation channel region is arranged below the body region, and wherein the desaturation channel region and the body region adjoin each other.

### Claim 10

A method of operating a semiconductor device comprising a first electrode terminal, a second electrode terminal, a gate electrode terminal, and a first IGBT cell including a gate electrode, a first electrode, a second electrode and a drift region, the gate electrode being connected to the gate electrode terminal, the first electrode is connected to the first electrode terminal, and the second electrode is connected to the second electrode terminal, the semiconductor device further comprising a desaturation semiconductor structure including a desaturation channel, a first portion of the desaturation semiconductor structure being connected to the first electrode terminal and a second portion of the desaturation semiconductor structure is connected to the gate electrode terminal for controlling the desaturation channel, the method comprising:
applying a gate voltage with a first value to the gate electrode terminal, wherein a current flows through the first IGBT cell between the first electrode terminal and the second electrode terminal and wherein a current flow through the desaturation channel is substantially blocked;
applying the gate voltage with a second value to the gate electrode terminal, the absolute value of the second value being lower than the absolute value of the first value, wherein a current flows through the first IGBT cell between the first electrode terminal and the second electrode terminal and wherein charge carriers flow as a desaturating current from the drift region of the first IGBT cell through the desaturation channel of the desaturation semiconductor structure to the first electrode terminal; and
applying the gate voltage with a third value to the gate electrode terminal, the absolute value of the third value being lower than the respective absolute values of the first and second values, wherein a current flow through the first IGBT cell between the first electrode terminal and the second electrode terminal is substantially blocked.

### Claim 11 (depends on 10)

The method according to claim 10, wherein the drift region of the first IGBT cell is second-type doped, and the desaturation semiconductor structure comprises: a first-type doped region forming a pn-junction with the second-type doped drift region of the first IGBT cell, two portions of a trench or two trenches arranged in the first-type doped region and arranged beside the first IGBT cell in a lateral direction, each of the two trench portions or each of the two trenches having a narrow part and a wide part below the narrow part, the wide parts confining a first-type doped desaturation channel region of the first-type doped region at least in the lateral direction and the narrow parts confining a first-type doped mesa region of the first-type doped region at least in the lateral direction, wherein the desaturation channel region has a width smaller than the mesa region in the lateral direction, and wherein the desaturation channel region and the mesa region adjoin each other.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the semiconductor device comprises a conductive semiconductor material in the two trench portions or in the two trenches, wherein the first-type doped mesa region is the first portion connected to the first electrode terminal, and the conductive semiconductor material is the second portion connected to the gate electrode terminal.

### Claim 13

A method of forming a bottleneck-type trench structure of a semiconductor device, the method comprising:
forming a trench in a semiconductor layer having lateral sides and a bottom side;
introducing a dopant into the bottom side;
heating the semiconductor device to diffuse the dopant into a diffusion region; and
selectively etching the diffusion region to form the bottleneck-type trench structure.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
oxidizing the diffusion region,
wherein selectively etching the diffusion region comprises selectively etching the oxidized diffusion region.

### Claim 15 (depends on 13)

The method of claim 13, further comprising:
oxidizing all sides of the bottleneck-type trench structure for providing an oxide layer; and
filling the bottleneck-type trench structure at least partly with a conductive semiconductor material,
wherein the oxide layer provides insulation between the conductive semiconductor material in the bottleneck-type trench structure and the semiconductor layer.

### Claim 16 (depends on 13)

The method of claim 13, further comprising:
doping all sides of the bottleneck-type trench structure to provide a separation layer; and
filling the bottleneck-type trench structure at least partly with a conductive material,
wherein the semiconductor layer has a first-type doping and the separation layer has a second-type doping for providing a separation between the conductive semiconductor material in the bottleneck-type trench structure and the semiconductor layer.

### Claim 17 (depends on 13)

The method of claim 13, wherein selectively etching the diffusion region comprises selectively etching the diffusion region in an acid etching solution comprising HNO3 and HF.

### Claim 18 (depends on 13)

The method of claim 13, wherein forming the trench in the semiconductor layer comprises etching the trench with a trench etch mask, and wherein introducing the dopant into the bottom side comprises implanting the dopant into the dopant side using the trench etch mask or using an implantation mask different from the trench etch mask.

### Claim 19 (depends on 13)

The method of claim 13, wherein heating the semiconductor device to diffuse the dopant into the diffusion region comprises heating the semiconductor device to a heating temperature for a heating time period, the heating temperature being in the range of from 800° C. to 1300° C., and the heating time period being in the range of from 60 min to 600 min, wherein the size of the diffusion region is controlled by the introduced dose of the dopant, of the heating temperature and of the heating time period.

### Claim 20 (depends on 13)

The method of claim 13, further comprising:
forming a dummy trench in the semiconductor layer having lateral sides and a bottom side;
introducing the dopant into the bottom side of the dummy trench;
heating the semiconductor device for diffusing the dopant into a diffusion region of the dummy trench;
selectively etching the diffusion region of the dummy trench;
detecting a detection material while selectively etching the diffusion region of the dummy trench; and
stopping the selective etching of the diffusion region of the trench when the detection material is detected.