# US 2014/0197875 A1 · Circuits and methods for signal interference mitigation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197875 A1 - Document ID: US20140197875A1 - Status: Published application - Kind: A1 - Application number: 13/739,256 - Filed: 2013-01-11 - Published: 2014-07-17 - Earliest claimed: 2013-01-11 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Sreenath Narayanan Potty; Jasbir Singh Nayyar; Vivek Singhal - Web page: https://patentgrep.com/patent/US20140197875A1 ## CPC - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - H04B 15/04: the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04B: TRANSMISSION ## Abstract Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit. ## Claims ### Claim 1 A signal interference mitigation circuit comprising: a clock divider circuit configured to generate a first clock signal, for clocking a digital circuit, based on a second clock signal and a division factor pattern; and a control circuit coupled with the clock divider circuit, the control circuit configured to: determine the division factor pattern, the division factor pattern comprising a plurality of division factors selected randomly based on a plurality of random numbers, and the division factor pattern being determined in a manner so as to control a throughput frequency associated with the signal interference mitigation circuit, and provide the division factor pattern to the clock divider circuit. ### Claim 2 A signal interference mitigation circuit comprising: a clock divider circuit configured to generate a first clock signal based on a second clock signal and a division factor pattern, wherein the clock divider circuit comprises: a multiplexer circuit configured to receive a selection signal from the control circuit and provide a selection of a division factor based on the division factor pattern and the selection signal; a counter configured to receive the selection of the division factor and generate the second clock signal indicative of a count value; a first comparator circuit coupled with the counter and the multiplexer circuit, the first comparator circuit configured to compare the selection of the division factor with the count value of the counter at the rate of the generated second clock signal and generate a trigger signal based on the comparison; and a flip-flop circuit coupled with the first comparator circuit and configured to receive the trigger signal and generate the first clock signal based on the division factor pattern; and a control circuit coupled with the clock divider circuit, the control circuit configured to: determine the division factor pattern, the division factor pattern comprising a plurality of division factors selected randomly based on a plurality of random numbers, and the division factor pattern being determined in a manner so as to control a throughput frequency associated with the signal interference mitigation circuit, and provide the division factor pattern to the clock divider circuit. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the control circuit comprises: a random number generator circuit clocked by the generated first clock signal and configured to generate a random number; a second comparator circuit communicatively associated with the random number generator circuit and configured to compare the random number with a predetermined threshold to generate the selection signal based on the comparison; and a register communicatively associated with the second comparator circuit and configured to store a value of the predetermined threshold. ### Claim 4 (depends on 3) The circuit of claim 3, wherein the control circuit further comprises: a plurality of counter circuits communicatively associated with the second comparator circuit, each of the plurality of counter circuits corresponding to one of the plurality of division factors, and the plurality of counter circuits configured to receive the selection signal and to count a selection of the corresponding one of the plurality of division factors; and a third comparator circuit communicatively associated with the plurality of counter circuits and the register and configured to compare a plurality of counts associated with the plurality of counter circuits based on a predetermined criterion so as to adjust the predetermined threshold in the register based on the comparison, the predetermined criterion being associated with the throughput frequency of the signal interference mitigation circuit. ### Claim 5 (depends on 3) The circuit of claim 3, wherein the random number generator circuit is a linear feedback shift register. ### Claim 6 An integrated circuit configured to mitigate signal interference, the integrated circuit comprising: a victim circuit operating in a predetermined frequency range; an aggressor circuit coupled with the victim circuit and capable of being operated on a first clock signal within the predetermined frequency range of the victim circuit; and a signal interference mitigation circuit coupled with the aggressor circuit, the signal interference mitigation circuit comprising: a clock divider circuit configured to generate the first clock signal, for clocking a digital circuit, based on a division factor pattern and a second clock signal, and a control circuit coupled with the clock divider circuit, the control circuit configured to: determine the division factor pattern, the division factor pattern comprising a plurality of division factors selected randomly based on a plurality of random numbers, and the division factor pattern being determined in a manner so as to control a throughput frequency associated with the signal interference mitigation circuit, and provide the division factor pattern to the clock divider circuit. ### Claim 7 An integrated circuit configured to mitigate signal interference, the integrated circuit comprising: a victim circuit operating in a predetermined frequency range; an aggressor circuit coupled with the victim circuit and capable of being operated on a first clock signal within the predetermined frequency range of the victim circuit; and a signal interference mitigation circuit coupled with the aggressor circuit, the signal interference mitigation circuit comprising: a clock divider circuit configured to generate the first clock signal based on a division factor pattern and a second clock signal, wherein the clock divider circuit comprises: a multiplexer circuit configured to receive a selection signal from the control circuit and to provide a selection of a division factor based on the division factor pattern and the selection signal; a counter configured to receive the selection of the division factor and to generate the second clock signal indicative of a count value; a first comparator circuit communicatively associated with the counter and the multiplexer circuit, the first comparator circuit configured to compare the selection of the division factor with the count value of the counter at the rate of the generated second clock signal and generate a trigger signal based on the comparison; and a flip-flop circuit communicatively associated with the comparator circuit and configured to receive the trigger signal and generate the first clock signal based on the division factor pattern; and a control circuit coupled with the clock divider circuit, the control circuit configured to: determine the division factor pattern, the division factor pattern comprising a plurality of division factors selected randomly based on a plurality of random numbers, and the division factor pattern being determined in a manner so as to control a throughput frequency associated with the signal interference mitigation circuit, and provide the division factor pattern to the clock divider circuit. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein the control circuit comprises: a random number generator circuit clocked by the generated first clock signal and configured to generate a random number; a second comparator circuit communicatively associated with the random number generator circuit and configured to compare the random number with a predetermined threshold to generate the selection signal based on the comparison; and a register communicatively associated with the second comparator circuit configured to store a value of the predetermined threshold. ### Claim 9 (depends on 8) The integrated circuit of claim 8, wherein the control circuit further comprises: a plurality of counter circuits communicatively associated with the second comparator circuit, each of the plurality of counter circuits corresponding to one of the plurality of division factors, and the plurality of counter circuits configured to receive the selection signal and to count a selection of the corresponding one of the plurality of division factors; and a third comparator circuit communicatively associated with the plurality of counter circuits and the register and configured to compare a plurality of counts associated with the plurality of counter circuits based on a predetermined criterion so as to adjust the predetermined threshold in the register based on the comparison, the predetermined criterion being associated with the throughput frequency of the signal interference mitigation circuit. ### Claim 10 (depends on 8) The integrated circuit of claim 8, wherein the random number generator circuit is a linear feedback shift register. ### Claim 11 (depends on 6) The integrated circuit of claim 6, wherein the aggressor circuit comprises at least one of a global positioning system circuit, a frequency modulation circuit, a short range wireless communications circuit, a wireless local area network circuit, and a near field communication circuit. ### Claim 12 (depends on 6) The integrated circuit of claim 6, wherein the victim circuit comprises at least one of a global positioning system circuit, a frequency modulation circuit, a short range wireless communications circuit, a wireless local area network circuit, and a near field communication circuit. ### Claim 13 A method for mitigating signal interference of at least one aggressor circuit, the at least one aggressor circuit capable of being operated on a first clock signal in an Integrated Circuit (IC) within an interfering frequency range of at least one victim circuit in the IC, the method at a signal interference mitigation circuit comprising: generating a second clock signal; determining a division factor pattern for dividing the second clock signal, the division factor pattern comprising a plurality of division factors selected randomly based on a plurality of random numbers, the division factor pattern being determined in a manner so as to control a throughput frequency of the signal interference mitigation circuit; and generating the first clock signal, for clocking a digital circuit, based on a division of the second clock signal by the plurality of division factors according to the division factor pattern. ### Claim 14 A method for mitigating signal interference of at least one aggressor circuit, the at least one aggressor circuit capable of being operated on a first clock signal in an Integrated Circuit (IC) within an interfering frequency range of at least one victim circuit in the IC, the method at a signal interference mitigation circuit comprising: generating a second clock signal; determining a division factor pattern for dividing the second clock signal, the division factor pattern comprising a plurality of division factors selected randomly based on a plurality of random numbers, the division factor pattern being determined in a manner so as to control a throughput frequency of the signal interference mitigation circuit, wherein determining the division factor pattern comprises: generating a plurality of random numbers, by a random number generator, the random number generator being actuated by the first clock signal, wherein each of the plurality of random numbers are updated at a clock edge of the first clock signal; comparing the generated random number with a predetermined threshold; and determining a frequency of occurrence of each division factor from among the plurality of division factors based on comparison; and generating the first clock signal based on a division of the second clock signal by the plurality of division factors according to the division factor pattern. ### Claim 15 (depends on 14) The method of claim 14, further comprising: tracking a number of selection of each of the plurality of division factors; comparing the tracked number of selection of each of the plurality of division factors based on a predetermined criterion, the predetermined criterion being associated with the throughput frequency; and performing increasing or decreasing of the predetermined threshold based on the comparison for controlling the throughput frequency. ### Claim 16 (depends on 15) The method of claim 15, wherein tracking comprises: counting the number of selection of each of the plurality of division factors by a plurality of counter circuits, such that each of the plurality of counter circuits corresponds to one of the plurality of division factors and each of the plurality of counter circuits is configured to count a selection of the corresponding one of the plurality of division factors. ### Claim 17 (depends on 13) The method of claim 13, further comprising: generating a selection signal indicative of a selection of a division factor from among the plurality of division factors associated with the division factor pattern. ### Claim 18 (depends on 14) The method of claim 14, wherein the random number generator circuit is a linear feedback shift register. ### Claim 19 (depends on 13) The method of claim 13, wherein the aggressor circuit comprises at least one of a global positioning system circuit, a frequency modulation circuit, a short range wireless communications circuit, a wireless local area network circuit, and a near field communication circuit. ### Claim 20 (depends on 13) The method of claim 13, wherein the victim circuit comprises at least one of a global positioning system circuit, a frequency modulation circuit, a short range wireless communications circuit, a wireless local area network circuit, and a near field communication circuit. ### Claim 21 (depends on 1) The circuit of claim 1, wherein a frequency of the first clock signal is equal to a frequency of the second clock signal divided by a random number. ### Claim 22 (depends on 6) The circuit of claim 6, wherein a frequency of the first clock signal is equal to a frequency of the second clock signal divided by a random number. ### Claim 23 (depends on 13) The method of claim 13, wherein a frequency of the first clock signal is equal to a frequency of the second clock signal divided by a random number.