# US 2014/0197873 A1 · Semiconductor Device

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- Number: US 2014/0197873 A1
- Document ID: US20140197873A1
- Status: Published application
- Kind: A1
- Application number: 14/211,426
- Filed: 2014-03-14
- Published: 2014-07-17
- Earliest claimed: 2011-05-20
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Tatsuji Nishijima
- Web page: https://patentgrep.com/patent/US20140197873A1

## CPC

- H03K 19/0175: Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00)
- G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence)
- H03K 19/018507: {Interface arrangements}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An object of one embodiment of the present invention to provide a latch circuit includes a level shifter and a buffer in which transistors each including a channel region formed in an oxide semiconductor film are connected in series. Thus, data can be held in the latch circuit even when power is not supplied.

## Claims

### Claim 1

(canceled)

### Claim 2

A semiconductor device comprising:
a level shifter;
a first buffer; and
a second buffer,
wherein the first buffer comprises a first transistor and a second transistor connected in series,
wherein the second buffer comprises a third transistor and a fourth transistor connected in series,
wherein the level shifter comprises a fifth transistor, a sixth transistor, and a seventh transistor connected in series and an eighth transistor, a ninth transistor, and a tenth transistor connected in series,
wherein a gate of the second transistor, a gate of the third transistor, and a gate of the eighth transistor are electrically connected to each other,
wherein a gate of the first transistor, a gate of the fourth transistor, and a gate of the fifth transistor are electrically connected each other,
wherein a gate of the sixth transistor and a gate of the seventh transistor are electrically connected to a connection portion of one of a source and a drain of the first transistor and one of a source and a drain of the second transistor, and
wherein a gate of the ninth transistor and a gate of the tenth transistor are electrically connected to a connection portion of one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, and
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor, and the tenth transistor are n-channel transistors.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein each of the first transistor to the fourth transistor comprises an oxide semiconductor in a channel region.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein the oxide semiconductor comprises indium.

### Claim 5 (depends on 2)

The semiconductor device according to claim 2, wherein the fifth transistor, the sixth transistor, the eighth transistor, and the ninth transistor are p-channel transistors.

### Claim 6 (depends on 2)

The semiconductor device according to claim 2, wherein a first inverter comprises the sixth transistor and the seventh transistor.

### Claim 7 (depends on 2)

The semiconductor device according to claim 2, wherein a second inverter comprises the ninth transistor and the tenth transistor.

### Claim 8 (depends on 2)

The semiconductor device according to claim 2,
wherein the other of the source and the drain of each of the first transistor and the third transistor is electrically connected to a wiring for supplying high power supply potential, and
wherein the other of the source and the drain of each of the second transistor and the fourth transistor is electrically connected to a wiring for supplying low power supply potential.

### Claim 9

A semiconductor device comprising:
a level shifter;
a first buffer;
a second buffer;
a first switch; and
a second switch;
wherein the first buffer comprises a first transistor and a second transistor connected in series,
wherein the second buffer comprises a third transistor and a fourth transistor connected in series,
wherein the level shifter comprises a fifth transistor, a sixth transistor, and a seventh transistor connected in series and an eighth transistor, a ninth transistor, and a tenth transistor connected in series,
wherein a connection portion of one of a source and a drain of the sixth transistor and one of a source and a drain of the seventh transistor is electrically connected to a gate of the second transistor, a gate of the third transistor, and a gate of the eighth transistor via the first switch,
wherein a connection portion of one of a source and a drain of the ninth transistor and one of a source and a drain of the tenth transistor is electrically connected to a gate of the first transistor, a gate of the fourth transistor, and a gate of the fifth transistor via the second switch,
wherein a gate of the sixth transistor and a gate of the seventh transistor are electrically connected to a connection portion of one of a source and a drain of the first transistor and one of a source and a drain of the second transistor,
wherein a gate of the ninth transistor and a gate of the tenth transistor are electrically connected to a connection portion of one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, and
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor, and the tenth transistor are n-channel transistors.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein each of the first transistor to the fourth transistor comprises an oxide semiconductor in a channel region.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, wherein the oxide semiconductor comprises indium.

### Claim 12 (depends on 9)

The semiconductor device according to claim 9, wherein the fifth transistor, the sixth transistor, the eighth transistor, and the ninth transistor are p-channel transistors.

### Claim 13 (depends on 9)

The semiconductor device according to claim 9, wherein a first inverter comprises the sixth transistor and the seventh transistor.

### Claim 14 (depends on 9)

The semiconductor device according to claim 9, wherein a second inverter comprises the ninth transistor and the tenth transistor.

### Claim 15 (depends on 9)

The semiconductor device according to claim 9,
wherein the other of the source and the drain of each of the first transistor and the third transistor is electrically connected to a wiring for supplying high power supply potential, and
wherein the other of the source and the drain of each of the second transistor and the fourth transistor is electrically connected to a wiring for supplying low power supply potential.

### Claim 16

A semiconductor device comprising:
a level shifter;
a first buffer;
a second buffer;
a first switch;
a second switch;
a first terminal;
a second terminal configured to receive an inverted signal of a signal input to the first terminal; and
a third terminal configured to receive a clock signal for controlling states of the first switch and the second switch,
wherein the first buffer comprises a first transistor and a second transistor connected in series,
wherein the second buffer comprises a third transistor and a fourth transistor connected in series,
wherein the level shifter comprises a fifth transistor, a sixth transistor, and a seventh transistor connected in series and an eighth transistor, a ninth transistor, and a tenth transistor connected in series,
wherein a connection portion of one of a source and a drain of the sixth transistor and one of a source and a drain of the seventh transistor is electrically connected to a gate of the second transistor, a gate of the third transistor, and a gate of the eighth transistor via the first switch,
wherein a connection portion of one of a source and a drain of the ninth transistor and one of a source and a drain of the tenth transistor is electrically connected to a gate of the first transistor, a gate of the fourth transistor, and a gate of the fifth transistor via the second switch,
wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the ninth transistor,
wherein a gate of the sixth transistor and a gate of the seventh transistor are electrically connected to a connection portion of one of a source and a drain of the first transistor and one of a source and a drain of the second transistor,
wherein a gate of the ninth transistor and a gate of the tenth transistor are electrically connected to a connection portion of one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor, and
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the seventh transistor, and the tenth transistor are n-channel transistors.

### Claim 17 (depends on 16)

The semiconductor device according to claim 16, wherein each of the first transistor to the fourth transistor comprises an oxide semiconductor in a channel region.

### Claim 18 (depends on 17)

The semiconductor device according to claim 17, wherein the oxide semiconductor comprises indium.

### Claim 19 (depends on 16)

The semiconductor device according to claim 16, wherein the fifth transistor, the sixth transistor, the eighth transistor, and the ninth transistor are p-channel transistors.

### Claim 20 (depends on 16)

The semiconductor device according to claim 16, wherein a first inverter comprises the sixth transistor and the seventh transistor.

### Claim 21 (depends on 16)

The semiconductor device according to claim 16, wherein a second inverter comprises the ninth transistor and the tenth transistor.

### Claim 22 (depends on 16)

The semiconductor device according to claim 16,
wherein the other of the source and the drain of each of the first transistor and the third transistor is electrically connected to a wiring for supplying high power supply potential, and
wherein the other of the source and the drain of each of the second transistor and the fourth transistor is electrically connected to a wiring for supplying low power supply potential.