# US 2014/0197872 A1 · Level shifter device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0197872 A1 - Document ID: US20140197872A1 - Status: Published application - Kind: A1 - Application number: 14/154,272 - Filed: 2014-01-14 - Published: 2014-07-17 - Earliest claimed: 2013-01-17 - Assignees: STMicroelectronics S.r.l. - Applicants: STMicroelectronics S.r.l. - Inventors: Agatino Antonino Alessandro - Web page: https://patentgrep.com/patent/US20140197872A1 ## CPC - H03K 19/0175: Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00) - H03K 3/35613: {the input circuit having a differential configuration} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A level shifter includes a first terminal configured to receive a first supply voltage, a second terminal configured to receive a second supply voltage, an input terminal configured to receive an input signal and an output terminal. The level shifter is configured to shift the input signal from the level of the first supply voltage to the level of the second supply voltage in outputting the output signal. The level shifter includes a storage circuit for storing the output signal value and configured, when the first supply voltage is no longer available, to force the output terminal to assume the last output voltage value stored by the storage circuit when the first supply voltage was available and before the first supply voltage was not available. ## Claims ### Claim 1 A level shifter device, comprising: a first terminal configured to receive a first supply voltage, a second terminal configured to receive a second supply voltage, an input terminal configured to receive an input signal, an output terminal, said level shifter device configured to shift the input signal from the level of the first supply voltage to the level of the second supply voltage outputting an output signal at the output terminal, wherein said level shifter device comprises: a storage circuit configured to store the output signal value and configured, when the first supply voltage is no longer available, to force the output terminal to assume a last output voltage value stored by the storage circuit when the first supply voltage was available and before the first supply voltage was not available. ### Claim 2 (depends on 1) The level shifter device according to claim 1, wherein the storage circuit is a latch comprising a first inverter, having an input terminal connected to a first internal circuit node and an output terminal connected to a second internal circuit node, and a second inverter, cascaded to the first inverter, having an input terminal connected to the second internal circuit node and an output terminal, which is the output terminal of the latch, connected to the first internal circuit node, said second internal circuit node being coupled with the output terminal of the level shifter so as to assume the same value of said output signal, said first and second inverters being coupled between the second supply voltage and a reference voltage. ### Claim 3 (depends on 2) The level shifter device according to claim 2, wherein said level shifter comprises a first pull-down component and a second pull-down component configured, when the first supply voltage is no longer available, to pull-down respectively the first internal circuit node or the second internal circuit node in accordance with the high or low value of the last output voltage value stored by the storage circuit when the first supply voltage was available. ### Claim 4 (depends on 3) The level shifter device according to claim 3, wherein the first pull-down component and the second pull-down component are transistors and the latch is configured to drive a drivable terminal of a first pull-down component through the first internal node and a drivable terminal of a second pull-down component through the second internal node. ### Claim 5 (depends on 4) The level shifter device according to claim 4, wherein the level shifter comprises another inverter having an input terminal connected to the input terminal of the differential cell and the output terminal connected to the drivable terminal of the second transistor of the differential cell, said another inverter being coupled between the first supply voltage and ground. ### Claim 6 (depends on 2) The level shifter device according to claim 2, wherein the level shifter comprises a differential cell including a first transistor coupled between the first internal circuit node and the reference voltage and a second transistor connected between the second internal circuit node and the reference voltage, a drivable terminal of the first transistor being the input terminal of the level shifter, the first pull-down component and the second pull-down component being configured, when the first supply voltage is no longer available, to pull-down respectively the first internal circuit node or the second internal circuit node by respectively acting on the drive terminals of the second or first transistor of the differential cell. ### Claim 7 (depends on 2) The level shifter device according to claim 2, further comprising a further inverter arranged between the output terminal of the latch and the output terminal of the level shifter, said further inverter being coupled between the second supply voltage and the reference voltage. ### Claim 8 A circuit, comprising: a differential input stage having a first input configured to receiving an input digital signal and a second input configured to receive a complement of the input digital signal and further having differential outputs; a first inverter circuit powered from a relatively lower supply voltage node and configured to generate the complement of the input digital signal; a latch circuit powered from a relatively higher supply voltage node and having latch nodes coupled respectively to the differential outputs; and a second inverter circuit powered from the relatively higher supply voltage node and having an input coupled to one of said latched nodes. ### Claim 9 (depends on 8) The circuit of claim 8, further comprising: a first pull down circuit coupled between the first input and a reference supply node and controlled by said one of said latched nodes of the latch circuit; and a second pull down circuit coupled between the second input and said reference supply node and controlled by another one of said latched nodes of the latch circuit. ### Claim 10 (depends on 8) The circuit of claim 8, wherein said latch circuit comprises cross-coupled inverter circuits. ### Claim 11 A method of level shifting, comprising: differentially receiving an input digital signal referenced to a relatively lower supply voltage; latching an inverted logic state of the received input digital signal in a latch circuit referenced to a relatively higher supply voltage; and inverting an output of the latched inverted logic state output from the latch circuit using an inverting circuit referenced to the relatively higher supply voltage. ### Claim 12 (depends on 11) The method of claim 11, further comprising: selectively activating a first pull down circuit coupled between a first input of the differentially received input digital signal and a reference supply node in response to first logic state stored at a first latch node of the latch circuit; and selectively activating a second pull down circuit coupled between a second input of the differentially received input digital signal and said reference supply node in response to said first logic state stored at a second latch node of the latch circuit.