# US 2014/0197867 A1 · Circuits and Methods for Using a Flying-Adder Synthesizer as a Fractional Frequency Divider

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- Number: US 2014/0197867 A1
- Document ID: US20140197867A1
- Status: Published application
- Kind: A1
- Application number: 13/741,118
- Filed: 2013-01-14
- Published: 2014-07-17
- Earliest claimed: 2013-01-14
- Assignees: Liming Xiu
- Inventors: Liming XIU
- Web page: https://patentgrep.com/patent/US20140197867A1

## CPC

- G06F 1/08: Clock generators with changeable or programmable clock frequency
- H03K 23/667: {by switching the base during a counting cycle}
- H03K 23/68: with a base which is a non-integer
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An open loop clock divider circuit includes (a) a first divider configured to receive an incoming clock signal and output a first divided clock signal, (b) a flying-adder synthesizer configured to fractionally divide the first divided clock signal and output a fractionally divided clock signal, and (c) a second divider configured to receive the fractionally divided clock signal and output a second divided clock signal. The open loop clock divider circuit advantageously provides a fractional divider in which there is no feedback loop between the source frequency (fs) and the destination frequency (fd). Methods of generating a divided clock signal involving the open loop clock divider circuit are also disclosed.

## Claims

### Claim 1

A fractional frequency divider, comprising:
a first divider configured to (i) receive an incoming clock signal and (ii) output a first divided clock signal;
a flying-adder synthesizer configured to (i) fractionally divide said first divided clock signal, and (ii) output a fractionally divided clock signal; and
a second divider configured to (i) receive said fractionally divided clock signal, and (ii) output a second divided clock signal.

### Claim 2 (depends on 1)

The divider of claim 1, wherein said incoming clock signal has a source frequency, said second divided clock signal has a destination frequency, and said destination frequency is said source frequency divided by (i) an integer of at least one and (ii) a fraction.

### Claim 3 (depends on 1)

The divider of claim 1, wherein said first divided clock signal has a plurality of phases.

### Claim 4 (depends on 3)

The divider of claim 3, wherein said plurality of phases are separated from each other by 2π/N degrees, N being an integer of at least 2.

### Claim 5 (depends on 3)

The divider of claim 3, wherein said flying-adder synthesizer receives said plurality of phases, and produces said fractionally divided clock signal from said plurality of phases.

### Claim 6 (depends on 5)

The divider of claim 5, wherein said flying-adder synthesizer produces said fractionally divided clock signal by selecting one of the plurality of phases at any given moment in accordance with a frequency control word.

### Claim 7 (depends on 6)

The divider of claim 6, having a division ratio fs/fd=F*N*M/K, where F is a numerical value represented by said multi-bit frequency word, N and M are each independently an integer of at least 2, K is the number of phases, fs is the source frequency of said incoming clock signal and fd is a destination frequency of said recovered clock signal.

### Claim 8 (depends on 7)

The divider of claim 7, wherein F=I+i, I is an integer of at least 1, and i is a fractional part of said frequency control word.

### Claim 9 (depends on 1)

The divider of claim 1, wherein said first frequency divider comprises a divide-by-N divider, and said second frequency divider comprises a divide-by-M divider.

### Claim 10 (depends on 9)

The divider of claim 9, wherein N and M are each independently an integer of at least 2.

### Claim 11 (depends on 9)

The divider of claim 9, wherein said divide-by-M divider is configured to perform fractional bit recovery.

### Claim 12

A method of generating a divided clock signal, comprising:
dividing an incoming clock signal to produce a first divided clock signal;
fractionally dividing the first divided clock signal in accordance with a multi-bit frequency word; and
dividing the fractionally divided clock signal to produce a second divided clock signal.

### Claim 13 (depends on 12)

The method of claim 12, further comprising outputting the second divided clock signal.

### Claim 14 (depends on 13)

The method of claim 13, wherein said incoming clock signal has a source frequency, said second divided clock signal has a destination frequency, and said destination frequency is said source frequency divided by (i) an integer of at least one and (ii) a fraction.

### Claim 15 (depends on 14)

The method of claim 14, wherein the integer and the fraction are defined by the multi-bit frequency word.

### Claim 16 (depends on 12)

The method of claim 12, wherein said first divided clock signal is generated by a first frequency divider, said first frequency divider having a divide-by ratio of N, N being an integer of at least 2.

### Claim 17 (depends on 12)

The method of claim 12, wherein said first divided clock signal is fractionally divided by a flying-adder synthesizer.

### Claim 18 (depends on 17)

The method of claim 17, further comprising generating said fractionally divided clock signal from said flying-adder synthesizer.

### Claim 19 (depends on 12)

The method of claim 12, wherein said fractionally divided clock signal is recovered by a second frequency divider.

### Claim 20 (depends on 19)

The method of claim 19, wherein said second frequency divider is a divide-by-M divider, M being an integer of at least 2.