# US 2014/0197864 A1 · Non-Volatile Latch Structures with Small Area for FPGA

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- Number: US 2014/0197864 A1
- Document ID: US20140197864A1
- Status: Published application
- Kind: A1
- Application number: 13/827,607
- Filed: 2013-03-14
- Published: 2014-07-17
- Earliest claimed: 2013-01-14
- Assignees: Cypress Semiconductor Corporation
- Applicants: Cypress Semiconductor Corporation
- Inventors: Venkatraman Prabhakar
- Web page: https://patentgrep.com/patent/US20140197864A1

## CPC

- H03K 19/0944: using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A latch circuit and method includes providing a first tri-gate non-volatile device, providing a second tri-gate non-volatile device, coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device, erasing the first tri-gate non-volatile device, programming the second tri-gate non-volatile device, and latching an output node of the latch device to a logic state determined by respective thresholds of the first and second tri-gate non-volatile devices. Coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device can include direct coupling, or indirect coupling through a cross-coupled circuit.

## Claims

### Claim 1

A latch circuit comprising:
a first non-volatile tri-gate device coupled between a source of supply voltage and an output node; and
a second non-volatile tri-gate device coupled between the output node and ground.

### Claim 2 (depends on 1)

The latch circuit of claim 1 wherein the first non-volatile tri-gate device comprises first and second MOS transistors, and a third transistor including a charge-trapping nitride layer.

### Claim 3 (depends on 2)

The latch circuit of claim 2 wherein the third transistor is coupled between the first and second transistors, and wherein each transistor shares a common current path.

### Claim 4 (depends on 1)

The latch circuit of claim 1 wherein the second non-volatile tri-gate device comprises first and second MOS transistors, and a third transistor including a charge-trapping nitride layer.

### Claim 5 (depends on 4)

The latch circuit of claim 4 wherein the third transistor is coupled between the first and second transistors, and wherein each transistor shares a common current path.

### Claim 6 (depends on 1)

The latch circuit of claim 1 wherein the first tri-gate device comprises two control gates and a programming gate.

### Claim 7 (depends on 1)

The latch circuit of claim 1 wherein the second tri-gate device comprises two control gates and a programming gate.

### Claim 8

A latch circuit comprising:
a first non-volatile tri-gate device coupled between a first node and a bit line;
a second non-volatile tri-gate device coupled between a second node and source line; and
a cross-coupled circuit coupled to a source of supply voltage and to the first and second nodes.

### Claim 9 (depends on 8)

The latch circuit of claim 8 wherein the first non-volatile tri-gate device comprises first and second MOS transistors, and a third transistor including a charge-trapping nitride layer.

### Claim 10 (depends on 9)

The latch circuit of claim 9 wherein the third transistor is coupled between the first and second transistors, and wherein each transistor shares a common current path.

### Claim 11 (depends on 8)

The latch circuit of claim 8 wherein the second non-volatile tri-gate device comprises first and second MOS transistors, and a third transistor including a charge-trapping nitride layer.

### Claim 12 (depends on 11)

The latch circuit of claim 11 wherein the third transistor is coupled between the first and second transistors, and wherein each transistor shares a common current path.

### Claim 13 (depends on 8)

The latch circuit of claim 8 wherein a first gate of the first tri-gate device and a first gate of the second tri-gate device are coupled together to a first control node.

### Claim 14 (depends on 13)

The latch circuit of claim 13 wherein a second gate of the first tri-gate device and a second gate of the second tri-gate device are coupled together to a programming node.

### Claim 15 (depends on 14)

The latch circuit of claim 14 wherein a third gate of the first tri-gate device and a third gate of the second tri-gate device are coupled together to a second control node.

### Claim 16 (depends on 8)

The latch circuit of claim 8 wherein the cross-coupled circuit comprises first and second cross-coupled MOS transistors.

### Claim 17 (depends on 8)

The latch circuit of claim 8 further comprising a buffer circuit coupled between the second node and an output node.

### Claim 18

A method of operating a latch circuit comprising:
providing a first tri-gate non-volatile device;
providing a second tri-gate non-volatile device;
coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device;
erasing the first tri-gate non-volatile device;
programming the second tri-gate non-volatile device; and
latching an output node of the latch device to a logic state determined by respective thresholds of the first and second tri-gate non-volatile devices.

### Claim 19 (depends on 18)

The method of claim 18 wherein coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device comprises direct coupling.

### Claim 20 (depends on 18)

The method of claim 18 wherein coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device comprises indirect coupling through a cross-coupled circuit.